Address/data queuing arrangement and method for providing high d

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

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710 52, G06F 1300

Patent

active

059419709

ABSTRACT:
An arrangement for transferring information between initiating and target buses, using contiguous command buffering and target bus command decoding. A bus interface bridge circuit includes an initiating bus interface which outputs a plurality of commands, where each of the commands includes a corresponding code. A memory queue is coupled to the initiating bus interface to receive the commands, and to contiguously store the commands into the registers of the queue. A target bus interface is coupled to the output of the memory queue to successively receive the commands. The commands are then executed at targeted devices in accordance with their corresponding codes. A method for transferring commands from an initiating bus to a target bus using contiguous command buffering and target bus command decoding is also provided.

REFERENCES:
patent: 4682304 (1987-07-01), Tierney
patent: 5546546 (1996-08-01), Bell et al.
"PCI Local Bus, PCI to PCI Bridge Architecture Specification", Apr. 5, 1994, pp. (i)-66.
"DECchip 21052 PCI-to-PCI Bridge Data Sheet", Digital Equipment Corporation, Order Number: EC-QHURA-TE, Jun. 1995, pp. (i)-A2.

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