Address counter control system with path switching

Electrical computers and digital processing systems: memory – Address formation – Incrementing – decrementing – or shifting circuitry

Reexamination Certificate

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Details

C711S104000, C711S105000, C711S154000, C711S217000, C711S165000, C365S222000

Reexamination Certificate

active

07017027

ABSTRACT:
An address-counter control system includes a counter circuit, path switches, and a control circuit. The counter circuit includes a first series of address counters which corresponds to a non-contiguous region portion and second and third series of address counters which correspond to respective contiguous region portions and which are located at two opposite ends of the first series of address counters. The path switches are provided at connection paths between the second and the third series of address counters. The path switches disconnect the first series of address counters and directly connect the second and third series of address counters or disconnect the direct connection between the second and third series of address counters and connect the first series of address counters to and between the second and the third series of address counters. The control circuit control the path switches.

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Seibert, On-chip refresh address counter circuit, Feb. 1982, IBM TDB, vol. 24 No 9, pp. 4673-4674.

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