Address counter and address counting method

Details Address counter and address counting method Address counter and address counting method

2001-12-27

2003-12-09

Bragdon, Reginald G. (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

C711S003000, C711S200000, C365S230010

Reexamination Certificate

active

06662290

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device; and, more particularly, to an address counter and address counting method capable of enhancing an operational speed by forming a path for outputting a corresponding output address as soon as an external or a previous internal address is inputted and generating both a path for the case when a parity signal having a high state is inputted and a path for the case when a parity signal having a low state is inputted. At the same time as producing the parity signal, the next internal address is immediately outputted in response to the generation of the parity signal.
BACKGROUND OF THE INVENTION
In general, existing DRAM, SRAM and flash memory devices employ a burst mode access function. Therefore, they need a circuit for counting addresses for the next data access operation inside the memory devices. As an operational speed of the memory devices goes faster, it is necessary to enhance an operational speed of the address counting circuit.
Conventional address counting schemes can be classified into two methods. Referring to
FIGS. 1 and 2
, there are shown schematic flow charts of the conventional address counting methods.
In
FIG. 1
, a flow chart of one example of the conventional address counting method is described, which receives an external address in step S
11
, latches the external address in step S
12
, generates a first parity corresponding to a first address in step S
13
before outputting the first address in step S
14
, and produces a second parity corresponding to a second address in step S
15
before outputting the second address in step S
16
.
In
FIG. 2
, a flow chart of the other example of the conventional address counting method is illustrated, which receives an external address in step S
21
, latches the external address in step S
22
at the same time of generating a first parity corresponding to a first address in step S
23
, outputs the first address in step S
24
, produces a second parity corresponding to a second address in step S
25
and, then, outputs the second address in step S
26
.
Referring to
FIG. 3
, a circuit diagram of a conventional address counter implemented as a unit block is depicted.
A first NAND gate
31
receives and logically combines an external column address signal, eyoz, and an inverted control signal outputted from a first inverter I
31
that inverts a control signal, seqx_intz, determining a counting scheme. An output signal of the first NAND gate
31
is transferred to a first latch circuit
33
through a first transmission gate T
31
, which operates in response to an address latch command signal, setz, and an inverted address latch command signal, setx.
The first latch circuit
33
includes a second inverter I
32
and a third inverter I
33
that operates in response to a next address generating signal, incx, and an inverted next address generating signal, incz, when a corresponding parity signal is inputted, and latches the output signal of the first NAND gate
31
.
An output signal of the first latch circuit
33
is inverted by a fourth inverter I
34
, which operates in response to the next address generating signal, incx, and the inverted next address generating signal, incz, when the parity signal is coupled, and then inputted to a second latch circuit
34
.
The second latch circuit
34
consists of a fifth inverter I
35
and a sixth inverter I
36
that operates in response to the next address generating signal, incx, and the inverted next address generating signal, incz, when the parity signal is provided, and latches an output signal of the fourth inverter I
34
. Further, the second latch circuit
34
outputs the latched signal as a first output signal onz.
Moreover, the output signal of the first NAND gate
31
transferred through the first transmission gate T
31
is delivered to an output node of the second latch circuit
34
through a second transmission gate T
32
that operates in response to the next address generating signal, incx, and the inverted next address generating signal, incz, when the parity signal is inputted, without passing through the first and the second latch circuits
33
and
34
.
Meanwhile, a second NAND gate
32
receives and logically combines the control signal, seqx_intz, and the external column address signal, eyoz. An output signal of the second NAND gate
32
is provided to a third latch circuit
35
through a third transmission gate T
33
that operates responsive to the address latch command signal, setz, and the inverted address latch command signal, setx.
The third latch circuit
35
is composed of an eighth inverter I
38
and a ninth inverter I
39
and latches the output signal of the second NAND gate
32
transferred through the third transmission gate T
33
. A tenth inverter I
40
inverts an output signal of the third latch circuit
35
and outputs the inverted signal as a first selection signal sel
1
. Moreover, the output signal of the third latch circuit
35
is produced as a second selection signal, sel
2
.
The output signal of the second latch circuit
34
is buffered by a seventh inverter I
37
and an eleventh inverter I
41
and, then, transferred through a fourth transmission gate T
34
. Further, the output signal of the second latch circuit
34
is inverted by the seventh inverter I
37
and, then, delivered through a fifth transmission gate T
35
.
The fourth and the fifth transmission gates T
34
and T
35
inversely operate in response to the first and the second selection signals, sel
1
and sel
2
. As a result, a signal transmitted through the fourth or the fifth transmission gate T
34
or T
35
is inverted by a twelfth inverter I
42
and, then, outputted as a second output signal, yacntz.
The address counting method depicted in
FIG. 1
shows a maximum operational speed of about 200 MHz while the other method explained in
FIG. 2
accomplishes a maximum operational speed of about 250 MHz. Therefore, there is no problem in the operational speed so far. However, for the next generation DRAM or SRAM devices, there will be required a faster operational speed of about several hundred MHz, so that there is a need to employ an address counter operating faster than the conventional address counters.
SUMMARY OF THE INVENTION
It is, therefore, a primary object of the present invention to provide an address counter and address counting method capable of enhancing an operational speed.
Another object of the present invention is to provide an address counter and address counting method having an operational speed applicable to the next generation memory devices.
The present invention forms a path for outputting a corresponding output address as soon as an external or a previous internal address is inputted and generates both of a path for the case a parity signal having a high state is inputted and that for the case the parity signal having a low state is provided. At the same time of producing the two paths, the parity signal is generated and the next internal address is immediately outputted in response to the generation of the parity signal. Further, an operation of latching the next address is also terminated as soon as the parity signal generated. That is, if a first address is generated, the next parity signal is produced and stands by ready, without control of an additional control signal, to allow a second address to be instantly outputted when it is required. Therefore, a whole operational speed of the address counter only depends on time required to output the parity signal and this time is about 1 ns, so that it is possible to achieve a maximum counting operation of about 1 GHz.
In accordance with an aspect of the present invention, there is provided an address counter comprising a plurality of address counting blocks, wherein each address counting block includes:
a first inverting unit for receiving and inverting an external address in response to a first control signal and an inverted first control signal;
a second inverting unit for receiving and inverting a previous internal address in resp

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