Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2001-11-20
2004-06-22
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S103000, C711S154000, C711S129000, C711S148000, C365S230030, C365S230060
Reexamination Certificate
active
06754797
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90122429, filed Sep. 11, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to an address converter apparatus for a memory chip, and more particularly, to an address converter apparatus and method for obtaining a memory controller application system that supports multiple memory chips.
2. Description of the Related Art
Due to the rapid development of memory chips, the controller application system that supports the old versions of memory chips has to be updated or replaced as the memory chips are upgraded. Similarly, the controller application system that supports the current versions of memory chips will face the same problem very soon. Therefore, the life cycle of the application system for memory chips is hard to estimate, and that causes inconvenience to the user. In addition, since the partition method of the current controller application system that supports the malfunctioning memory chip is limited, the damaged region cannot be isolated with a bank address partition method. The performance of the application system for isolating the damaged region of the memory chip is poor, and a lot of problems are caused.
SUMMARY OF THE INVENTION
The invention provides an address converter apparatus and method to support various kinds of memory chips to allow the controller application system that supports the old version of memory chip to also support the current version of memory chip, so that the life cycle of the controller application system is prolonged. Similarly, the controller application system that supports the current version of memory chip can support future versions of memory chips by using the apparatus and method provided by the present invention. In addition, the apparatus provided by the present invention can use different malfunctioning memory chip partition methods to resolve the poor efficiency problem of the current application system.
The invention provides an application system of an address converter apparatus to support various memory chips. The application system comprises a control chip, an addressing converter and a currently operating memory chip. The control chip outputs an address and chip select signal to control a first type memory chip. The current applied memory chip is one of either the first type memory chip, a second type memory chip, or a partly damaged first type memory chip. The addressing converter is coupled to the control chip and the currently operating memory chip to convert the address and chip select signal output by the control into an output address and chip select signal to control the currently operating memory chip.
The address converter apparatus that supports various memory chips comprises a select configuration and storage apparatus to configure and store a select configuration value of the currently operating memory chip, and a logic control and switch circuit. The logic control and switch circuit is coupled to the select configuration and storage apparatus, the control chip, and the currently operating memory chip to receive the address and chip select signal output by the control chip. According to the select configuration value, the address and chip select signal output by the control chip are converted into an output address and chip select signal by the logic control and switch circuit.
In the above decode converting apparatus that supports various memory chips, the logic control and switch circuit comprises a pass-through circuit, a chip partition circuit, a bank partition circuit for malfunctioning chip, a bank merge circuit and a switch circuit. The pass-through circuit is coupled to the control chip to directly conduct the address and chip select signal to the output address and chip select signal. The chip partition circuit is coupled to the control chip to partition and simulate the second memory chip into a plurality of the first type memory chips. The bank partition circuit for malfunctioning chip is coupled to the control chip to isolate the malfunctioning portion of the malfunctioning first type memory chips by bank partition, so as to obtain a half set of original memory chips. The bank merge circuit is coupled to the control chip to merge and simulate the isolated malfunctioning portions of the malfunctioning first type chips into a complete first type memory chip. The switch circuit is coupled to the pass-through circuit, the chip partition circuit, the bank partition circuit for malfunctioning chip, and the bank merge circuit, the select configuration and storage apparatus and the currently operating memory chip to select and output a correct output address and chip select signal among the pass-through circuit, the chip partition circuit, the bank partition circuit for malfunctioning chip, and the bank merge circuit to control the current operating circuit.
In a preferred embodiment of the present invention, the logic control and switch circuit further comprises a malfunctioning chip partition circuit coupled to the control chip and the switch circuit to partition the partly malfunctioning first type memory chip and to isolate the malfunctioning portion thereof. A memory chip with the same number of banks, and only a half capacity is obtained.
In the preferred embodiment of the present invention, the logic control and switch circuit further comprises a chip merge circuit coupled to the control chip and the switch circuit to merge and simulate the isolated partly malfunctioning first type memory chips into a complete first type memory chip in a row addressing manner.
In the preferred embodiment of the present invention, the logic control and switch circuit further comprises a bank address partition circuit coupled to the control chip and the switch circuit to partition and simulate the isolated partly malfunctioning first type memory chips into a memory chip with the complete bank number but half of the capacity.
In the preferred embodiment of the present invention, the logic control and switch circuit further comprises an inverse circuit coupled to the control chip and the switch circuit to invert the row address signal into an output row address signal.
The invention further comprises a converting method to support multiple kinds of memory chips to convert the address and chip select signal output by the control chip into an output address and chip select signal to control the currently operating memory chip. The currently operating memory chip includes one of either a first type memory chip, a second type memory chip, or a plurality of partly malfunctioning first type memory chips. The converting method includes selecting and storing a select configuration value of the currently operating memory chip, receiving the output address and chip select signal, and converting the output address and chip select signal into an output address and chip select signal to control the currently operating memory chip.
In the converting method to support multiple kinds of memory chips, when the currently operating memory chip is the first type memory chip, the address and chip select signal is directly conducted to the output address and chip select signal. When the currently operating memory chip is the second type memory chip, the second type memory chip is partitioned and simulated as a plurality of first type memory chips. When the currently operating memory chip is the partly malfunctioning first type memory chip, the malfunctioning portions thereof are partitioned by bank partition. The isolated malfunctioning first type memory chips are then merged and simulated into a complete first type memory chip.
It is known from the above that the invention uses a flexibly programmed memory addressing circuit as a bridge between the control chip and the memory chip. According to the select configuration value, a correct addressing method is selected to convert the address and chip select signal from the control chip into the output address and chip select signal, so as
Chuang Hai-Feng
Wu Kun-Ho
J.C. Patents
Leadtek Research Inc.
Peugh Brian R.
Sparks Donald
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