Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-10-07
2002-04-02
Beausoleil, Robert (Department: 2181)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C365S200000, C365S201000, C714S711000
Reexamination Certificate
active
06367030
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an address conversion circuit and an address conversion system. More particularly, the present invention relates to an address conversion circuit and an address conversion system for use with a memory which is provided with a redundant memory array for relieving defective memory cells so as to facilitate ensuring memory capacity.
2. Description of the Related Art
FIG. 6
illustrates a conventional address conversion system. The address conversion system includes a CPU
3
, a memory control circuit
110
connected to the CPU
3
, and a plurality of memories
102
connected to the memory control circuit
110
.
Memory is sold typically with a particular capacity (eg. 40 MB). This capacity is ensured, meaning that even if some memory cells are defective, the memory will still provide the designated capacity.
Each memory
102
includes a normal memory array (not shown) having a capacity corresponding to the total capacity of the memory
102
.
The memory
102
of the conventional address conversion system includes, in addition to the normal memory array, a redundant memory array (not shown) and a redundancy decision circuit
103
for ensuring the total capacity of the memory
102
even when the normal memory array includes a defective memory cell (not shown). When the defective memory cell is to be accessed, the redundancy decision circuit
103
replaces a physical address corresponding to the defective memory cell by another physical address corresponding to a memory cell in the redundant memory array.
FIG. 7
illustrates the memory
102
and the memory control circuit
110
of the conventional address conversion system in greater detail. For sake of simplicity, only one memory
102
is shown in FIG.
7
. The memory control circuit
110
includes an address conversion section
101
. The redundancy decision circuit
103
in the memory
102
includes a comparison circuit
102
A and a defective address storing section
102
B.
The address conversion circuit
101
converts a logical address received from the CPU
3
to a physical address corresponding to a memory cell in the memory
102
. The comparison circuit
102
A compares the physical address received from the address conversion circuit
101
with a defective address stored in the defective address storing section
102
B.
When the physical address received from the address conversion circuit
101
matches the defective address, the memory cell to be accessed is a defective memory cell. In such a case, the redundancy decision circuit
103
replaces the physical address received from the address conversion circuit
101
by a redundant address corresponding to a memory cell in the redundant memory array and accesses the memory cell in the redundant memory array instead of the defective memory cell.
When the physical address received from the address conversion circuit
101
does not match the defective address, the memory cell to be accessed is a normal memory cell. In such a case, the redundancy decision circuit
103
accesses the memory cell in the normal memory array corresponding to the physical address received from the address conversion circuit
101
.
As described above, the conventional address conversion system includes the redundancy decision circuit
103
in each memory
102
so that the redundancy decision is made within the memory
102
for ensuring the total capacity of the memories
102
even when a defective memory cell exists. In such an address conversion system, however, the access speed to the memory decreases for the reason described below.
FIG. 8A
illustrates a first processing method used in a memory access operation by the conventional address conversion system.
FIG. 8B
illustrates a second processing method used in a memory access operation by the conventional address conversion system.
Referring to
FIG. 8A
, in the first processing method, the redundancy decision circuit
103
first performs a process P
1
(over a time period T
1
) for determining whether a physical address received from the address conversion circuit
101
matches a defective address stored in the defective address storing section
102
B and, if there is a match, replacing the physical address with a redundant address. Subsequent to the process P
1
, a process P
2
(over a time period T
2
) is performed for accessing a memory cell corresponding to either the physical address from the address conversion circuit
101
(a normal address) or the redundant address by which the physical address from the address conversion circuit
101
is replaced.
Referring to
FIG. 8B
, in the second processing method, the process P
1
is performed as described above while performing, in parallel with the process P
1
, a process P
3
(over a time period T
3
) for making an access to a certain point in an access path to the memory cell corresponding to the normal address.
Subsequent to the process P
1
, if the redundancy decision circuit
103
in the memory
102
determines that the physical address received from the address conversion circuit
101
matches the defective address, a process P
4
(over the time period T
2
) is performed to access the memory cell corresponding to the redundant address with which the physical address from the address conversion circuit
101
is replaced.
If the redundancy decision circuit
103
determines that the physical address received from the address conversion circuit
101
does not match the defective address, the redundancy decision circuit
103
does not have to perform the address replacement process. In such a case, after a wait time T
5
(=T
1
−T
3
), a process P
6
(over a time period T
6
=T
2
−T
3
) is performed to complete access to the normal address part of which has been made during the process P
3
.
In either the first processing method or the second processing method, the accessing time (a time period from the time when the memory
102
receives a physical address to the time when the addressed data is accessed and output) necessarily includes the time period T
1
(for the redundancy decision circuit
103
to determine whether the physical address received from the address conversion circuit
101
matches a defective address and, if there is a match, replace the physical address by a redundant address).
Conventionally, in order to meet the demand to design a memory such that the memory independently ensures the total capacity thereof, the redundancy decision circuit
103
has been provided in the memory
102
. As a result, the time period T
1
(for determining whether the physical address received from the address conversion circuit
101
matches a defective address and, if there is a match, replacing the physical address by a redundant address) has been consumed by the memory
102
. This is disadvantageous, however, in terms of reducing the time required by the address conversion system to access the memory
102
.
SUMMARY OF THE INVENTION
According to one aspect of this invention, an address conversion circuit is provided for converting a logical address to a physical address and outputting the physical address to a memory, the memory including a normal memory array and a redundant memory array wherein a defective address corresponding to a defective memory cell in the normal memory array is replaced by a redundant address in the redundant memory array so as to ensure total memory capacity of the memory. The address conversion circuit includes: an address conversion section for converting the logical address to a first physical address in the normal memory array and outputting the first physical address; a defective address storing section for storing the defective address corresponding to the defective memory cell in the memory; and a redundancy decision circuit for, in response to a decision that the first physical address matches the defective address, replacing the first physical address with a second physical address corresponding to the redundant address and sending the second physical addr
Beausoleil Robert
Phan Raymond
Renner Otto Boisselle & Sklar
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