Address control system for segmented buffer memory

Details Address control system for segmented buffer memory Address control system for segmented buffer memory

1987-09-21

1990-02-27

Zache, Raulfe B.

Boots, shoes, and leggings

3649393, 3649269, 3649390, 3649330, G06F 1200, G06F 100

Patent

active

049051849

ABSTRACT:
A buffer memory in a peripheral controller has dedicated page and word location segments for each one of a multiple number of attached peripheral units. Additionally, an auxiliary segment provides memory for the active status of each one of the multiple number of data transfer cycle operations which may be occurring concurrently and which status can be accessed at the optimum time so that each initiated data transfer cycle can be completed in a time-saving fashion. Memory address control means are provided for accessing page segments and word locations therein in order to insert data therein or to remove data therefrom. A special queue segment is available to provide concurrent status information for each I/O command initiated by a host computer.

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patent: 4750107 (1988-06-01), Buggert et al.

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