Address control system for a RAM in a digital audio set

Details Address control system for a RAM in a digital audio set Address control system for a RAM in a digital audio set

1992-04-10

1994-03-22

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

365194, 36523002, 36523006, 365236, G11C 800

Patent

active

052971007

ABSTRACT:
An address control system for a RAM, comprising a synchronous counter for receiving input data according to a clock signal and providing n-bit row column address, and an n-bit column address a first buffer for receiving the n-bit row address from the synchronous counter and generating the n-bit row address, a first tri-state inverter for outputting data stored in a ROM according to a write enable signal a second tri-state inverter for outputting reference data according to the write enable signal, an adder for adding the n-bit column address from the synchronous counter and output address signals from the first inverter, and a second buffer for receiving output signals from the adder generating a column address delayed from the n-bit column address.

REFERENCES:
patent: 4506348 (1985-03-01), Miller et al.
patent: 4813014 (1989-03-01), DeBell
patent: 5173878 (1993-12-01), Sakui et al.

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