Address control circuit of semiconductor memory apparatus

Details Address control circuit of semiconductor memory apparatus Address control circuit of semiconductor memory apparatus

2011-04-05

2011-04-05

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S201000, C365S230080

Reexamination Certificate

active

07920437

ABSTRACT:
An address control circuit for a semiconductor memory apparatus so as to make a refresh operation test possible by designating a refresh address is presented. The circuit includes a buffer block, a decoder, and a latch block. The buffer block receives coding information coded testing address information in accordance to a test signal. The decoder generates a test refresh address by decoding the coding information. The latch block latches the test refresh address depending on the test signal.

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