Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
1998-03-17
2001-02-20
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700, C365S230060, C714S711000, C714S710000
Reexamination Certificate
active
06191982
ABSTRACT:
THE FIELD OF THE INVENTION
The present invention relates generally to integrated circuits, and more particularly to address compare schemes used to replace primary circuit elements with redundant circuit elements in memory integrated circuits, such as dynamic random access memories, static random access memories, video random access memories, and erasable programmable read only memories.
BACKGROUND OF THE INVENTION
Technological advances have permitted semiconductor integrated circuits to comprise significantly more circuit elements in a given silicon area. Reducing and eliminating defects in the circuit elements has, however, become increasingly more difficult with the increased number of circuit elements. To achieve higher population capacities, circuit designers strive to reduce the size of the individual circuit elements to maximize available die real estate. The reduced size makes these circuit elements increasingly susceptible to defects caused by material impurities during fabrication. Nevertheless, the defects are identifiable upon completion of the integrated circuit fabrication by testing procedures, either at the semiconductor chip level or after complete packaging. Scrapping or discarding defective integrated circuits when defects are identified is economically undesirable, particularly if only a small number of circuit elements are actually defective.
Relying on zero defects in the fabrication of integrated circuits is an unrealistic option. Therefore, redundant circuit elements are provided on integrated circuits to reduce the number of scrapped integrated circuits. If a primary circuit element is determined to be defective, a redundant circuit element is substituted for the defective primary circuit element. Substantial reductions in scrap are achieved by using redundant circuit elements without substantially increasing the cost of the integrated circuit.
One type of integrated circuit device which uses redundant circuit elements is integrated memory circuits, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), video random access memories (VRAMs), and erasable programmable read only memories (EPROMs). Typical integrated memory circuits comprise millions of equivalent memory cells arranged in arrays of addressable rows and columns. The rows and columns of memory cells are the primary circuit elements of the integrated memory circuit. By providing redundant circuit elements, either as rows or columns, defective primary rows or columns can be replaced.
Because the individual primary circuit elements (rows or columns) of an integrated memory circuit are separately addressable, replacing a defective circuit element typically comprises blowing fuse-type circuits to “program” a redundant circuit element to respond to the address of the defective primary circuit element. This process is very effective for permanently replacing defective primary circuit elements.
In the case of DRAMs, for example, a particular memory cell is selected by first providing a unique row address of the row in which the particular memory cell is located and subsequently providing a unique column address of the column in which the particular memory cell is located. Redundancy circuitry must recognize the address of the effective primary circuit element and reroute all signals to the redundant circuit element when the address to the defective primary circuit element is presented by the user. Therefore, a number of fuses are associated with each redundant circuit element. The possible combinations of blown and unblown fuses corresponding to each redundant circuit element represent unique addresses of all primary circuit elements for which a corresponding redundant circuit element may be substituted.
During testing of the DRAM at the factory, any defective primary circuit elements are identified. A suitable redundant circuit element is selected, and the corresponding fuses are blown in a predetermined order to represent the address of the defective primary circuit element to be replaced. When using the DRAM, each address provided to the DRAM must be compared to the corresponding fuses to determine if a redundant match is present. Whenever the redundant match is detected, the primary circuit element is suppressed and the redundant circuit element is activated to perform the required function. Since each row or column on a DRAM is selected by one of 2
n
binary combinations of high and low states on n address inputs, the compare of addresses to the fuses must compare all n address inputs to the combination of blown and unblown fuses to determine if a redundant match exists.
Various techniques have previously been utilized to facilitate the address/fuse compare. As will be apparent from the prior art discussion in the following detailed description of the preferred embodiments, the prior techniques have suffered from a variety of problems. Some previous address/fuse compare circuits occupy excessive silicon area and require excessive fanin into an overall match comparator circuit, which combines individual bit compares between portions of the address bits and the corresponding fuses. Other previous address/fuse compare circuits precharge a precharge node in the compare circuit to reduce silicon area and fanin, but the time required to precharge the precharge node prevents real time compares from occurring. Thus, an improved address/fuse compare scheme is needed for non-precharged redundancy address matching which causes a redundant circuit element to respond to the address of the defective primary circuit element.
SUMMARY OF THE INVENTION
The present invention provides an integrated circuit receiving n address bits and including primary circuit elements being selectable by binary values of the n address bits. A programmable master storage device stores and provides a programmable master condition which when active indicates that at least one primary circuit element is being replaced. The integrated circuit also includes redundant circuit elements, with each having a corresponding matching circuit. Each matching circuit includes a plurality of sub-match circuits. Each sub-match circuit includes programmable two state storage devices, which are programmable to a programmed state. In the programmed state one of the two state storage devices is in a first of the two states and the rest of the two state storage devices are in a second of the two states. Each two state storage device corresponds to one of the possible binary values of at least one of the n address bits. Each sub-match circuit is responsive to the master condition and a binary value of the at least one of the n address inputs to activate a sub-match signal when the binary value of the at least one of the n address bits corresponds to the one of the two state storage devices in the first state and the master condition is active. Each sub-match circuit includes redundancy disable circuitry responsive to a redundancy control signal being in a first state to deactivate an activated sub-match signal. A match circuit is coupled to the plurality of sub-match circuits for activating a match signal in response to all of the sub-match signals being active. The activated match signal is used to disable a primary circuit element from being selected by a corresponding binary value of the n address bits and to enable the redundant circuit element to be selected by the corresponding binary value of the n address bits.
The redundancy control signal is preferably controllable from external to the integrated circuit to permit a user of the integrated circuit according to the present invention to deactivate the match signal to prevent access by the associated redundant circuit element. This redundancy disable feature permits the user of the integrated circuit according to the present invention to disable redundancy in certain test modes; when it is determined that the redundant circuit element is not functioning properly; or for any other suitable reason. In one embodiment, the state of the redundancy control signal default
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
Tran Andrew Q.
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