Address coding method and address decoder for reducing...

Details Address coding method and address decoder for reducing... Address coding method and address decoder for reducing...

2007-02-20

2007-02-20

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S222000, C365S230060

Reexamination Certificate

active

11152449

ABSTRACT:
An address coding method, which is performed by a memory device including a plurality of banks each being shared by at least two memory blocks, includes: activating adjacent banks shared by at least two memory blocks during a refresh operation of the memory device, and enabling the refresh operation in each bank alternately between the at least two memory blocks. The method includes activating adjacent banks shared by the at least two memory blocks during another operation of the memory device, and enabling the another operation in each bank alternately between the at least two memory blocks.

REFERENCES:
patent: 5796669 (1998-08-01), Araki et al.
patent: 6366524 (2002-04-01), Abedifard
patent: 6373769 (2002-04-01), Kiehl et al.
patent: 6721223 (2004-04-01), Matsumoto et al.
patent: 6728257 (2004-04-01), Bharghavan et al.
patent: 0330982 (2003-01-01), None
English Abstract, Jan. 31, 2003 (See above).

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