Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Patent
1996-01-25
1997-06-17
Clawson, Jr., Joseph E.
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
365222, 365233, B11C 800
Patent
active
056403607
ABSTRACT:
An address buffer circuit for a semiconductor memory device includes first and second address inputs which are selectably connectable to a first node according to first and second address input control signals, respectively. The device also includes first and second switches which are controlled by a refresh mode signal and selectively output a first or second address enable signal. Further, a latch is provided which latches the address signal input to the first node, and outputs the latched address signal in periods of the selected first or second address enable signals.
REFERENCES:
patent: 5537564 (1996-07-01), Hazanchuk et al.
Han Jin-Man
Kim Gyu-hong
Kim Hyung-Dong
Clawson Jr. Joseph E.
Samsung Electronics Co,. Ltd.
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