Address buffer for synchronous system

Details Address buffer for synchronous system Address buffer for synchronous system

1996-02-08

1997-04-29

Hudspeth, David R.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 98, 36523008, H03K 19096

Patent

active

056253028

ABSTRACT:
A truc/complement receiver driver circuit in which the input signals may be applied prior to a sysnchronous clock signal. The input signals are sensed and latched to generate complementary output signals. The generation of the output signals causes the receiver portion of the circuit to be automatically reset for the next cycle. The leading edge of the systemclock causes the circuit outputs to reset and enables the receiver circuit to be enabled for the next cycle. Multiplexed input receiver circuits allow the circuit to respond to a plurality of input signal sources.

REFERENCES:
patent: 4189769 (1980-02-01), Cook et al.
patent: 5305282 (1994-04-01), Choi
patent: 5400295 (1995-03-01), Matsumura et al.
patent: 5534796 (1996-07-01), Edwards
patent: 5543731 (1996-08-01), Sigal et al.
patent: 5544101 (1996-08-01), Houston
patent: 5559453 (1996-09-01), Covino et al.

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