Address buffer circuit and method for controlling the same

Details Address buffer circuit and method for controlling the same Address buffer circuit and method for controlling the same

2005-09-21

2009-08-25

Hur, Jung (John) H. (Department: 2824)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S195000, C365S227000

Reexamination Certificate

active

07580318

ABSTRACT:
An address buffer circuit for a semiconductor memory device wherein an address buffer is enabled (to output an internal address signal) in response to a first level of a control signal and, but is disabled in response to a second level of the control signal. An address buffer control unit generates the control signal at the second level in ‘no operation’ state (NOP command) in which the semiconductor memory device does not perform data accessing operations and generates the control signal at the first level while the semiconductor memory device performs data accessing operations, thereby reducing or minimizing the output of an internal address buffered and output by the address buffer at and thus reducing power consumption during no-operation states of the semiconductor memory device.

REFERENCES:
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patent: 4787067 (1988-11-01), Takemae et al.
patent: 5124584 (1992-06-01), McClure
patent: 5384745 (1995-01-01), Konishi et al.
patent: 6295245 (2001-09-01), Tomita et al.
patent: 6363031 (2002-03-01), Phelan
patent: 6430092 (2002-08-01), Nanba
patent: 6519188 (2003-02-01), Ryoo et al.

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