Address buffer and semiconductor memory device using the same

Details Address buffer and semiconductor memory device using the same Address buffer and semiconductor memory device using the same

2002-11-22

2004-09-21

Auduong, Gene N. (Department: 2818)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S189050, C365S193000

Reexamination Certificate

active

06795369

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an address buffer and a semiconductor memory device having the same.
2. Description of Related Art
A conventional semiconductor memory device includes an address buffer comprising a normal address buffer unit for buffering addresses received from address pins in normal operation mode and a mode-setting signal buffer unit for buffering mode-setting signals received from the address pins in a mode-setting operational mode.
The conventional address buffer, however, involves a problem that the logic level of the mode-setting signals is transited in response to the logic level transition of the addresses input through the address pins in the normal operational mode, which increases current consumption. That is, the mode-setting signal buffer unit is actually operated during the normal operational mode, thereby undesirably consuming current.
FIG. 1
illustrates a conventional semiconductor memory device. The conventional semiconductor memory device comprises address pins
10
-
1
to
10
-
n
, command pins
12
-
1
to
12
-
3
, address buffers
14
-
1
to
14
-
n
, a chip selection signal (CSB) buffer
16
-
1
, a row address strobe signal (RASB) buffer
16
-
2
, a column address strobe signal (CASB) buffer
16
-
3
, an address decoder
18
, a mode-setting register
20
, a command decoder
22
and a PCLKR signal generating circuit
24
.
The address pins
10
-
1
to
10
-
n
receive external addresses A
1
to An. The command pins
12
-
1
,
12
-
2
and
12
-
3
receive command signals CSB, RASB, CASB, respectively. The address buffers
14
-
1
to
14
-
n
latch the external addresses A
1
to An in response to the PCLKR signal and generate buffered mode-setting signals MAB
1
to MABn. The address buffers
14
-
1
to
14
-
n
buffer the external addresses A
1
to An in response to the active command ACT and generate buffered addresses AB
1
to ABn. The address decoder
18
decodes the buffered addresses AB
1
to ABn and generates decoded addresses DAB
1
to DABm. The mode-setting register
20
receives the buffered mode-setting signals MAB
1
to MABn and outputs mode-setting signals MDAB
1
-MDABk in response to the mode-setting command MRS.
The CSB buffer
16
-
1
buffers the chip selection signal CSB and generates a buffered chip selection signal CSBB. The RASB buffer
16
-
2
buffers the row address strobe signal RASB and generates a buffered row address strobe signal RASBB. The CASB buffer
16
-
3
buffers a column address strobe signal CASB and generates a buffered column address strobe signal CASBB. The command decoder
22
decodes the buffered command signals CSBB, RASBB, CASBB and generates a mode-setting command MRS, an active command ACT, a pre-charge command PRE and a refresh command REF. The PCLKR signal generating circuit
24
generates the PCLKR signal in response to the buffered row address strobe signal RASBB.
FIG. 2
illustrates a circuit diagram of the address buffer comprising the normal address buffer unit
30
and the mode-setting signal buffer unit
32
. The normal address buffer unit
30
comprises inverters I
1
, I
2
, I
5
, I
6
and I
7
, complementary metal oxide semiconductor (CMOS) transmission gates C
1
and C
2
, and a latch L
1
comprising inverters I
3
and I
4
. The mode-setting signal buffer unit
32
comprises an inverter I
8
, a CMOS transmission gate C
3
, a PMOS transistor P and a latch L
2
comprising inverters I
9
and I
10
.
In
FIG. 2
, references A, AB, MAB, ACT denote an external address externally input, a buffered address, a mode-setting signal and an active command, respectively. The PCLKR signal is a clock signal generated in response to the row address strobe signal RASB of logic “low” level. A reference VCCH denotes a voltage that maintains a logic “high” level upon power-up and is then transited to a logic “low” level.
The inverter I
1
inverts the external address A. The CMOS transmission gate C
1
is turned on in response to the PCLKR signal of logic “low” level, thereby transmitting an output signal of the inverter I
1
to the latch L
1
. The latch L
1
latches and inverts an output signal of the CMOS transmission gate C
1
. The CMOS transmission gate C
2
is turned on in response to the active command of a logic “high” level, thereby transmitting an output signal of the latch L
1
. The inverters
16
and
17
buffer an output signal of the CMOS transmission gate C
2
, thereby generating the buffered address AB.
The inverter I
8
inverts the output signal of the latch L
1
. The CMOS transmission gate C
3
is turned on in response to the signal PCLKR of logic “high” level, thereby transmitting an output signal of the inverter I
8
. The PMOS transistor P is turned on in response to the VCCH signal of logic “low” level after power-up and when the voltage of a node n equals the power supply voltage. The latch L
2
is reset by the PMOS transistor P, thereby generating the mode-setting signal MAB of a logic “low” level. Further, the latch L
2
generates the mode-setting signal of a logic “low” level when a signal of a logic “high” level is transmitted from the CMOS transmission gate C
3
to the latch L
2
. Conversely, latch L
2
generates the mode-setting signal of logic “high” level when a signal of logic “low” level is transmitted.
Therefore, in the normal operation mode that the active command ACT, the pre-charge command PRE or the refresh command REF is applied to the semiconductor memory device, the CMOS transmission gate C
1
is turned on in response to the PCLKR signal of a logic “low” level generated in response to row address strobe signal RASB, so that the external address A is transmitted to the latch L
1
via the inverter I
1
. When the signal PCLKR of the logic “low” level is transited to the logic “high” level, the CMOS transmission gate C
3
is turned on and a signal, i.e., the address A, latched in the latch L
1
, is transmitted via the inverter I
8
and the CMOS transmission gate C
3
to the latch L
2
.
Accordingly, the mode-setting signal MAB is transited from a logic “low” level to a logic “high” level along with the logic level transition of the address A during the normal operation mode, thereby causing undesired current consumption.
FIG. 3
is a timing diagram illustrating operation of the address buffer in
FIG. 2
, wherein the address A is transited from a logic “low” level to a logic “high” level.
When the row address strobe signal RASB of a logic “low” level and the address A transiting from a logic “low” level to a logic “high” level are externally input to the semiconductor memory device at rising edge of a clock signal CLK, the PCLKR signal is generated in response to the row address strobe signal RASB. The CMOS transmission gate C
1
transmits the address A to the latch L
1
in response to the PCLKR signal of a logic “low” level. The CMOS transmission gate C
3
transmits the signal output from the latch L
1
to the latch L
2
in response to the PCLKR signal of a logic “high” level. Accordingly, current is consumed by the address buffer because the mode-setting signal MAB is transited from a logic “low” level to a logic “high” level along with level transition of the address A in the normal operation mode. Further, if the active command ACT of a logic “high” level is generated, the CMOS transmission gate C
2
is turned on and generates the buffered address AB rising up from a logic “low” level to a logic “high” level.
Worse, such current consumption by the mode-setting signal buffer unit increases as the number of the address buffers increases.
SUMMARY OF THE INVENTION
To overcome the problems described above, a preferred embodiment of the present invention provides an address buffer wherein a mode-setting signal is not changed in response to logic level of an address externally input during a normal operation mode, thereby reducing current consumption, and a semiconductor memory device utilizing such an address buffer.
In accordance with one aspect of the present invention, there is provided an address buffer comprising: a fi

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