Address Buffer

Details Address Buffer Address Buffer

1982-03-03

1984-05-29

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Data refresh

365189, G11C 1140

Patent

active

044519087

ABSTRACT:
An address buffer for a dynamic memory includes a flip-flop. The flip-flop is coupled at its one input/output terminal with both a first input circuit and a third input circuit connected in parallel with each other and at its other input/output terminal with a second input circuit. The second input circuit receives a reference voltage and is activated by an external address timing clock during a normal operation mode. The first input circuit is also activated by the external address timing clock, but receives an external address. The third input circuit receives an internal refresh address and is activated by an internal refresh address. The address buffer cooperates with a switcher which produces the internal refresh address timing clock and the external address timing clock, alternatively, by switching a basic timing clock generated by an address drive clock generator.

REFERENCES:
patent: 3737879 (1973-06-01), Greene

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