Address bit latching input circuit

Details Address bit latching input circuit Address bit latching input circuit

1996-04-10

1997-12-30

Hudspeth, David R.

Electronic digital logic circuitry

Interface

326 86, 326105, 36523008, 365227, H03K 190175

Patent

active

057034990

ABSTRACT:
An input circuit for a memory address bit operates at high operating speed. A PMOS transistor 112 is provided between a supply line for 1/2V.sub.CC and a node N11. When not in operation, node N11 of input portion 11A is precharged not to the power supply voltage V.sub.CC, but to 1/2V.sub.CC, a potential halfway between the power supply voltage V.sub.CC and 0 V. Another PMOS transistor 117 is provided between a PMOS transistor 111 and node N11 of the input stage to prevent leakage between V.sub.CC and 1/2V.sub.CC. As a result, an enable signal ENB goes to a high level, the circuit enters the operating state, address bit signal Ai is input, and the time needed to shift the level of node N11 to V.sub.CC or 0 V becomes short.

REFERENCES:
patent: 5319262 (1994-06-01), Cederbaum et al.
patent: 5402387 (1995-03-01), Hotta
patent: 5469402 (1995-11-01), Yamauchi et al.
patent: 5586081 (1996-12-01), Mills et al.
patent: 5610862 (1997-03-01), Teels

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