Address and data transfer circuit

Details Address and data transfer circuit Address and data transfer circuit

2000-03-23

2003-02-04

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S211000

Reexamination Certificate

active

06516392

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an address and data transfer circuit required for a hierarchical multi-port memory comprising a plurality of single-port memories.
2. Description of the Related Art
In order to implement a single-chip system having advanced processing functions such as audio and/or video processing or language translation, it is essential to obtain a high data-processing bit rate. Therefore, it will be required in future that the achievable data-processing bandwidth is as high as decades or hundreds times of that possible at the present time. To fulfill such requirement, a multi-port memory having an access bandwidth on the order of tera bits (10
12
bits) per second should be used instead of a single-port memory estimated to have a practical limit of about 50 Gbit/s. The access bandwidth of the tera bits per second order can be realized in the multi-port memory having 32 ports whose word length is 64 bit for each port under a practical clock frequency of 500 MHz, for example.
When constructing a conventional multi-port memory, a large circuit area is required and it is thus difficult to utilize the multi-port memory as a practical mass storage device. In view of such difficulty, a hierarchical multi-port memory has been proposed as described, for example, in H. J. Mattausch: “Hierarchical N-Port Memory Architecture based on 1-Port Memory Cells”, Proc. 23rd European Solid-State Circuits Conf., Southampton, UK, September, pp. 348-351, 1997. Such a multi-port memory is comprised of single-port memories, and thus requires only a small circuit area.
However, as the hierarchical multi-port memory should have a data input/output function and a function for selectively connecting the external ports to the single-port memories, it is required to have an address and data transfer circuits, which are not necessary for any other conventional multi-port memory.
DISCLOSURE OF THE INVENTION
It is therefore an object of the present invention to provide an address and data transfer circuit required for a hierarchical multi-port memory with a very small occupied area and capable of achieving an access bandwidth on the tera bits per second order.
According to the present invention, there is provided an address and data transfer circuit comprising: enable circuit means for enabling a single-port memory in accordance with an access requirement from a corresponding port out of a plurality of external ports; active address selecting circuit means, responsive to activation of the enabling circuit means, for selecting an address from the corresponding port and transferring the address to the single port memory; and active data selecting circuit means, responsive to activation of the enabling circuit means, for selecting a data from the corresponding port and transferring the data to or from the single port memory.
With the above-mentioned arrangement according to the invention, the hierarchical multi-port memory with a very small occupied area and an access bandwidth of the tera bits per second order can be realized.
Preferably, the enable circuit means comprises: enabling circuits to which selection signals are input from the corresponding port, and from which an address selection signal is output to the active address selecting circuit means, respectively; operating circuits to which a read/write signal from the corresponding port and the address selection signal are input, and from which a read signal and a write signal based on the read/write signal and also on the address selection signal are output to the active data selecting circuit means, respectively; a first OR gate to which a plurality of the address selection signals are input, and from which a logical sum of the address selection signals is output to the active address selecting circuit means and the single-port memory; and a second OR gate to which a plurality of the write signals are input, and from which a logical sum of the write signals is output to the single-port memory.
Preferably, active address selecting means comprises a multiplexer for multiplexing the address signals and inputting the multiplexed address signals to the single-port memory.
Preferably, active data circuit means comprises: a multiplexer for multiplexing the data and outputting the multiplexed data to the single-port memory; and a demultipexer for demultiplexing the data from the single-port memory and outputting the demultiplexed data to the corresponding port.


REFERENCES:
patent: 5542067 (1996-07-01), Chappell et al.
patent: 5619674 (1997-04-01), Ikumi
patent: 6212607 (2001-04-01), Miller
Koji et al.,A Development Of Multi-port Memory With Small Area Based On A New Hierarchical Architecture, The Institute of Electronics, Information and Communication Engineers, Mar. 25 to 28, 1999.

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