Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-03-01
1998-06-02
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711126, 71180023, 71180041, G06F 1200
Patent
active
057617139
ABSTRACT:
An address aggregation system enhances the performance of a processor that executes instructions out of order by enhancing the throughput of data addressing from the processor to a remote data cache (DCACHE). In essence, the processor is configured to concurrently address separate independent DCACHE banks, each preferably an inexpensive single ported random access memory (RAM), during each processor cycle. In the preferred implementation, the DCACHE has odd and even banks that are addressed by respective odd and even data addresses during each processor cycle. The processor comprises an instruction cache (ICACHE), an instruction fetch mechanism (IFETCH) for retrieving instructions from the ICACHE, a sort mechanism (SORT) for receiving instructions from the IFETCH and for sorting the instructions into arithmetic instructions and memory instructions, and a memory queue (MQUEUE) for receiving the memory instructions from the sort and permitting the instructions to execute out of order. The MQUEUE includes a plurality of address reorder buffer slots (ARBSLOTs), an odd bank arbitrator, and an even bank arbitrator. Each of the ARBSLOTs maintains an address, determines whether the address is odd or even, and generates a respective odd or even request depending upon whether the address is odd or even. The odd and even bank arbitrators receive the requests associated with the odd and even addresses respectively and control the ARBSLOTS to output data to the DCACHE.
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Chow Christopher S.
Hewlett-Packard Co.
Swann Tod R.
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