Address accessed memory device having parallel to serial convers

Details Address accessed memory device having parallel to serial convers Address accessed memory device having parallel to serial convers

1982-02-05

1984-05-22

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Sipo/piso

365189, G11C 1300

Patent

active

044505388

ABSTRACT:
A memory device is provided with first and second memories. Two groups of data are loaded into the first and second memories, through a data buffer register. The same address information is applied to the first and second memories and the information is read out from the first and second memories. The two groups of the data read out in parallel are applied to a data multiplexer which in turn converts the parallel information into the serial one.

REFERENCES:
patent: 3560940 (1971-02-01), Gaensslen
patent: 3763480 (1973-10-01), Weimer
patent: 3863232 (1975-01-01), Johnson et al.

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