Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-07
2004-11-23
Thomes, Tom (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S335000, C257S336000, C257S339000, C257S344000, C257S345000, C257S347000, C257S348000, C257S349000, C257S355000, C257S357000, C257S358000, C257S361000, C257S362000
Reexamination Certificate
active
06822297
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related in general to the field of electronic systems and semiconductor devices, and more specifically to structure and fabrication methods of short-channel MOS transistors, which have an additional implant under the LDD/pocket compared to standard technology.
DESCRIPTION OF THE RELATED ART
Integrated circuits (ICs) may be severely damaged by electrostatic discharge (ESD) events. A major source of ESD exposure to ICs is from the charged human body (“Human Body Model”, HBM); the discharge of the human body generates peak currents of several amperes to the IC for about 100 ns. A second source of ESD is from metallic objects (“machine model”, MM); it can generate transients with significantly higher rise times than the HBM ESD source. A third source is described by the “charged device model” (CDM), in which the IC itself becomes charged and discharges to ground in the opposite direction than the HBM and MM ESD sources. More detail on ESD phenomena and approaches for protection in ICs can be found in A. Amerasekera and C. Duvvury, “ESD in Silicon Integrated Circuits” (John Wiley & Sons LTD. London 1995), and C. Duvvury, “ESD: Design for IC Chip Quality and Reliability” (Int. Symp. Quality in El. Designs, 2000, pp. 251-259; references of recent literature).
ESD phenomena in ICs are growing in importance as the demand for higher operating speed, smaller operating voltages, higher packing density and reduced cost drives a reduction of all device dimensions. This generally implies thinner dielectric layers, higher doping levels with more abrupt doping transitions, and higher electric fields—all factors that contribute to an increased sensitivity to damaging ESD events.
The most common protection schemes used in metal-oxide-semiconductor (MOS) ICs rely on the parasitic bipolar transistor associated with an NMOS device whose drain is connected to the pin to be protected and whose source is tied to ground. The protection level or failure threshold can be set by varying the NMOS device width from the drain to the source under the gate oxide of the NMOS device. Under stress conditions, the dominant current conduction path between the protected pin and ground involves the parasitic bipolar transistor of that NMOS device. This parasitic bipolar transistor operates in the snapback region under pin positive with respect to ground stress events.
The dominant failure mechanism, found in the NMOS protection device operating as a parasitic bipolar transistor in snapback conditions, is the onset of second breakdown. Second breakdown is a phenomenon that induces thermal runaway in the device wherever the reduction of the impact ionization current is offset by the thermal generation of carriers. Second breakdown is initiated in a device under stress as a result of self-heating. The peak NMOS device temperature, at which second breakdown is initiated, is known to increase with the stress current level.
Many circuits have been proposed and implemented for protecting ICs from ESD. One method that is used to improve ESD protection for ICs is biasing the substrate of ESD protection circuits on an IC. Such substrate biasing can be effective at improving the response of a multi-finger MOS transistor that is used to conduct an ESD discharge to ground. However, substrate biasing can cause the threshold voltages for devices to change from their nominal values, which may affect device operation. In addition, substrate biasing under steady-state conditions causes heat generation and increases power losses.
Solutions offered in known technology require additional IC elements, silicon real estate, and/or process steps (especially photomask alignment steps). Their fabrication is, therefore, expensive. Examples of device structures and methods are described in U.S. Pat. No. 5,539,233, issued Jul. 23, 1996 (Amerasekera et al., “Controlled Low Collector Breakdown Voltage Vertical Transistor for ESD Protection Circuits”); U.S. Pat. No. 5,793,083, issued Aug. 11, 1998 (Amerasekera et al., “Method for Designing Shallow Junction, Salicided NMOS Transistors with Decreased Electrostatic Discharge Sensitivity”); U.S. Pat. No. 5,940,258, issued Aug. 17, 1999 (Duvvury, “Semiconductor ESD Protection Circuit”); U.S. Pat. No. 6,137,144, issued Oct. 10, 2000, and U.S. Pat. No. 6,143,594, issued Nov. 7, 2000 (Tsao et al, “On-Chip ESD Protection in Dual Voltage CMOS); and U.S. patent application Ser. No. 09/456,036, filed Dec. 12, 1999 (Amerasekera et al., “Electrostatic Discharge Device and Method”).
The influence of substrate well profiles on the device ESD performance is investigated, for instance, in “Influence of Well Profile and Gate Length on the ESD Performance of a Fully Silicided 0.25 &mgr;m CMOS Technology” (K. Bock, C. Russ, G. Badenes, G. Groeseneken and L. Deferm, Proc. EOS/ESD Symp., 1997, pp. 308-315). However, known technology recommends only a lower epitaxial doping or a lower implant dose as methods to increase the p-well resistance. These approaches are especially insufficient when the channel length of MOS transistors is progressively reduced, driven by the continuing miniaturization trend.
The challenge of cost reduction implies a drive for minimizing the number of process steps, especially a minimum number of photomask steps, and the application of standardized process conditions wherever possible. These constraints should be kept in mind when additional process steps or new process conditions are proposed to improve ESD insensitivity without sacrificing any desirable device characteristics. An urgent need has, therefore, arisen for a coherent, low-cost method of enhancing ESD insensitivity without the need for additional, real-estate consuming protection devices. The device structure should further provide excellent electrical performance, mechanical stability and high reliability. The fabrication method should be simple, yet flexible enough for different semiconductor product families and a wide spectrum of design and process variations. Preferably, these innovations should be accomplished without extending production cycle time, and using the installed equipment, so that no investment in new manufacturing machines is needed.
SUMMARY OF THE INVENTION
A short-channel NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a channel stop region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate, and both having a depletion region when reverse biased. The shallow regions are surrounded in part by an enhanced p-doping implant pocket. The transistor further has in these regions of enhanced p-doping another region of a p-resistivity higher than the remainder of the semiconductor. These regions extend laterally approximately from the inner border of the respective shallow region to the inner border of the respective recessed region, and vertically from a depth just below the depletion regions of source and drain to approximately the top of the channel stop regions.
According to the invention, these regions of higher p-type resistivity are created after gate definition by an ion implant of compensating n-doping, such as arsenic or phosphorus, using the same photomask already used for implants creating the extended source and drain and the pockets of enhanced p-doping.
In an ESD event, these regions of higher resistivity increase the current gain of the parasitic lateral npn bipolar transistor and thus raise the current It
2
, which initiates the thermal breakdown with its destructive localized heating, thereby improving ESD robustness.
When the gate, source and substrate terminals are at 0 V and the drain at positive potential, the current gain &bgr; of the lateral bipolar npn transistor in the ESD event is defined as
&bgr;=(
Id−Igen
)/(
Igen−Isub
),
where
Id=drain current,
Igen=Ib+Isub,
Ib=base current,
Isub=hole current from the collector junction through the substrate to the backs
Kim Young-min
Nandakumar Mahalingam
Zhao Song
Brady III W. James
Ortiz Edgardo
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Thomes Tom
LandOfFree
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