Additional gate control for a double-gate MOSFET

Details Additional gate control for a double-gate MOSFET Additional gate control for a double-gate MOSFET

2005-04-05

2005-04-05

Vu, Hung (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000, C257S366000

Reexamination Certificate

active

06876042

ABSTRACT:
A FinFET includes a fin formed on an insulating layer and a first gate material layer formed proximate to sides of the fin. The FinFET further includes a protective layer formed above the first gate material layer and the fin, and a second gate material layer formed above the protective layer and the fin. The second gate material layer may be formed into a gate for the fin that may be biased independently of gate(s) formed from the first gate material layer, thus providing additional design flexibility in controlling the potential in the fin during on/off switching of the FinFET.

REFERENCES:
patent: 4979014 (1990-12-01), Hieda et al.
patent: 6359311 (2002-03-01), Colinge et al.
patent: 6433609 (2002-08-01), Voldman
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6657252 (2003-12-01), Fried et al.
patent: 6812119 (2004-11-01), Ahmed et al.
patent: 20020003255 (2002-01-01), Usuki et al.
patent: 20020125536 (2002-09-01), Iwasa et al.
patent: 20020153587 (2002-10-01), Adkisson et al.
patent: 20020177263 (2002-11-01), Hanafi et al.
patent: 20030042531 (2003-03-01), Lee et al.
patent: 20030113970 (2003-06-01), Fried et al.
patent: 20040075121 (2004-04-01), Yu et al.
patent: 0 623 963 (1994-11-01), None
Jong-Tae Park et al.: “Multiple-Gate SOI MOSFETs: Device Design Guidelines,”IEEE Transactions on Electron Devices,vol. 49, No. 12, Dec. 2002, pp. 2222-2229.
Fu-Liang Yang et al.: “25 nm CMOS Omega FETs,” International Electron Devices Meeting 2002, IEDM, Technical Digest, Dec. 8-11, 2002 in New York, NY, pp. 255-258.
Toshikazu Mukaiyama et al.: “Fabrication of Gate-All-Around MOSFET By Silicon Anisotropic Etching Technique,”Solid State Electronics,Elsevier Science Publishers, vol. 42, No. 7-8, Jul. 8, 1998, pp. 1623-1626.
Yang-Kyu Choi et al.: “Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era, ”Solid State Electronics,Elsevier Science Publishers, vol. 46, No. 10, Oct. 2002, pp. 1595-1601.
Effendi Leobandung et al.: “Wire-channel and wrap-around-gate metal-oxide-semiconductor field-effect transistors with a significant reduction of short channel effects,” 41stInternational Conference on Electron, Ion, and Photon Beams Technology and Nanofabrication in Dana point, CA, May 27-30, 1997, vol. 15, No. 6,Journal of Vacuum Science&Technology B(Microelectronics and Nonometer Structures), Nov.-Dec. 1997, AIP for American Vacuum Soc., pp. 2791-2794.
PCT International Search Report mailed Jul. 13, 2004, 5 pages.
PCT International Search Report, Apr. 8, 2004, 3 pages.
Digh Hisamoto et al.: “FinFet—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al.: “Sub-20nm CMOS Fin Fet Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al.: “Sub-50 nm P-Channel Fin FET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Yang-Kyu Choi et al.: “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
Xuejue Huang et al.: “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Co-pending Appl. No. 10/348,758, filed Jan. 23, 2003, entitled “Germanium MOSFET Devices and Methods for Making Same,” 22 page specification, 29 sheets of drawings.
Co-pending Appl. No. 10/274,961, filed Oct. 22, 2002, entitled “Double and Triple Gate MOSFET Devices and Methods for Making Same,” 15 page specification, 12 sheets of drawings.

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