Adding plug-in unit slots to a high capacity bus

Details Adding plug-in unit slots to a high capacity bus Adding plug-in unit slots to a high capacity bus

1999-10-19

2002-03-12

Beausoleil, Robert (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S107000, C370S402000

Reexamination Certificate

active

06356967

ABSTRACT:

FIELD OF THE INVENTION
This invention concerns such a data transmission bus in plug-in unit and rack systems wherein plug-in units are connected to the bus when pushed into the rack, so that the plug-in units can be in data transmission connection with one another through the bus.
BACKGROUND OF THE INVENTION
Relatively complex distributed equipment environments, such as telecommunication equipment and computer systems, use different backplane buses, the purpose of which is to connect the different units electrically and mechanically to each other and to allow prompt communication between the units. The buses may be passive buses or they may be active ones, wherein the peripheral logic speeds up voltage level changes in the bus and thus makes the bus operate faster.
Backplane buses may also be used in systems formed by several hardware racks, such as e.g. in the node device of a digital telecommunication system, where data and clock signals must be transmitted between hardware racks. For timing, digital systems need synchronising signals commonly called clocks. E.g. in such backplane bus systems wherein exactly simultaneous timing information is required, distribution of clocks is carried out in the way shown in
FIG. 1
by constructing a star-like transmission line network containing several parallel transmission lines
11
of equal length. For each transmission line there is the line's own transmitter
12
, to which the clock is supplied from a clock source
13
common to all transmission lines. At the end of each transmission line there is the line's own receiver
14
for reception of the clock. Drawbacks of this kind of solution (caused by several parallel transmitter/receiver couples) are relatively high costs and difficult implementation of the construction among other equipment, e.g. inflexibility in situations where changes occur. For example, the place of an individual transmitter can not be moved anywhere in practice, because cabling can not be drawn from anywhere so that the transmission lines will be of equal length.
If exactly simultaneous timing information is not a necessary feature, Bus Transceiver Logic (BTL) circuits have been used in backplane buses e.g. in a structure according to the Futurebus standard, wherein one transmitter supplies a common bus to which several receivers are connected. A first drawback of this solution is that propagation delays are different with different receivers. Under these circumstances, the timing information is not sufficiently exact for all applications, but the solution is suitable in those cases only where exactly simultaneous timing information is not a necessary feature. In addition, the power consumption is high in the system due to parallel termination at both ends of the bus.
Due to increasing clock frequencies and a growing complexity of the equipment, backplane buses have become one of the major factors limiting system performance. If those parameters which are critical to the backplane bus, that is, delay, noise and noise tolerance, are poorly predicted, then the performance determined for the system will not be achieved. The specific impedance of the backplane bus is an important factor affecting system performance and design. It affects important parameters such as propagation delay, noise tolerance, connection noise, internal capacitance and cross-talk. In theory, the specific impedance will not affect the propagation delay of a signal propagating on the bus, but taking into account those capacitances of equipment connected to the bus which connect in parallel with the specific impedance and thus increase the total impedance, a slower bus operation will result.
With a reduced specific impedance the internal bus capacitance and thus the signal rise time will grow. A rise time delay is thus mainly caused by the backplane bus, but it is also caused by the charging delay of plug-in unit controllers connected to the backplane bus which increases the total delay.
FIG. 2
shows a bus B, which is located in the rear part of an equipment cabinet and to which N plug-in units are connected through transmitter/receiver blocks. The bus end mounts a plug-in unit supplying such a master clock to the bus with which the other plug-in units of the bus will synchronise. Due to the grounds mentioned above, the bus has a certain clock frequency so that at frequencies exceeding this delays will grow so much that unit C, which is located at the other end of the bus and to which unit A at the opposite end sends a signal in its transmission time slot, will receive the signal so late that a part of the signal or the whole signal will drift outside the reception time slot.
By using a quick bus interface in the plug-in units, so-called GTL technology, the bus clock frequency may be increased to some extent. The Gunning Transceiver Logic (GTL) using Low-Voltage-Swing (LVS) CMOS transistors has been developed especially to allow integration of transmitter/receiver for Very Large-Scale Integration (VLISI) and ASIC circuits instead of the transmitter/receiver being a separate module as in traditional plug-in units. By using GTL technology a maximum number of ten plug-in units may be connected to the passive bus B located in the rear part of the equipment cabinet.
When using GTL technology, the transmitter/receiver capacitance of the plug-in unit is approximately 10-15 pF. When plug-in units are added so that their number is more than ten, the result is that the bus impedance will vary between 25 and 80&OHgr;, whereby the bus is never fully adapted. In consequence, when the clock pulse amplitude has risen, there will be oscillation caused by interference in the signal, and the units will have to wait until the oscillations have passed by.
It should also be noticed that the master clock located at one end of the bus will cause phase skew of the clock on the long bus.
One solution of problems caused by transmission delays is presented in the applicant's Finnish Patent Application FI-953010, inventor Voutilainen Martti. The idea there is to supply a step-less essentially sinusoidal waveform to the bus through such an adapter circuit which besides adapting the level of the propagating wave essentially at the desired level, also absorbs the reflection returning from the transmission line and at the same time prevents multiple reflections. Such a waveform similar to a standing wave is hereby obtained in the transmission line, which is formed as the sum of the propagating and once reflected wave and which may be used for system timing and also for information transmission. With the method it is possible in practice to eliminate almost entirely that timing difference between different receivers which is caused by propagation delay.
FIG. 3
shows a system in accordance with the patent application mentioned above in its simplest embodiment. Series resistor R
1
is connected to the output of low output impedance sine wave generator
31
so that its opposite pole is connected to transmission line
32
, to which receivers
33
of the individual equipment units are connected at different points. Of the individual equipment units ( e.g. of the backplane's plug-in units) the figure shows only the receiver, because equipment units may be of very many different types and because the structure of the equipment unit does not belong within the scope of the invention. The value of series resistance R
1
is essentially the same as the effective impedance of the transmission line, that is, the transmission line impedance in the loaded state (receiver circuits connected to the transmission line). The transmission line end is open and, in addition, the length of the transmission line is shorter than one-fourth of the wave length. In the most advantageous case the transmission line length is approximately equal to ⅛
th
of the wave length. The receivers are hereby in an area where the amplitude of the transmission line signal is close to its maximum, irrespective of where they are located on the transmission line. If the transmission line length

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