Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-05-28
2002-11-05
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C712S015000, C712S017000, C712S200000
Reexamination Certificate
active
06477697
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to systems and techniques for designing programmable processing elements such as microprocessors and the like. More specifically, the invention is directed to the design of an application solution containing one or more processors where the processors in the system are configured and enhanced at the time of their design to improve their suitability to a particular application. In particular, the present invention is directed to a system in which application developers can rapidly develop instruction extensions, such as new instructions, to an existing instruction set architecture, including new instruction which manipulate user-defined processor state, and immediately measure the impact of the extension to the application run time and to the processor cycle time.
2. Background of the Related Art
Processors have traditionally been difficult to design and to modify. For this reason, most systems that contain processors use ones that were designed and verified once for general-purpose use, and then used by multiple applications over time. As such, their suitability for a particular application is not always ideal. It would often be appropriate to modify the processor to execute a particular application's code better (e.g., to run faster, consume less power, or cost less). However, the difficulty, and therefore the time, cost, and risk of even modifying an existing processor design is high, and this is not typically done.
Another difficulty with prior art processor design stems from the fact that it is not appropriate to simply design traditional processors with more features to cover all applications, because any given application only requires a particular set of features, and a processor with features not required by the application is overly costly, consumes more power and is more difficult to fabricate. In addition, it is not possible to know all of the application targets when a processor is initially designed. If the processor modification process could be automated and made reliable, then the ability of a system designer to create application solutions would be significantly enhanced.
Because the processor cannot easily be enhanced, many system designers do not attempt to do so, and instead choose to execute an inefficient pure-software solution on an available general-purpose processor. The inefficiency results in a solution that may be slower, or require more power, or be costlier (e.g., it may require a larger, more powerful processor to execute the program at sufficient speed). Other designers choose to provide some of the processing requirements in special-purpose hardware that they design for the application, such as a coprocessor, and then have the programmer code up access to the special-purpose hardware at various points in the program. However, the time to transfer data between the processor and such special-purpose hardware limits the utility of this approach to system optimization because only fairly large units of work can be sped up enough so that the time saved by using the special-purpose hardware is greater than the additional time required to transfer data to and from the specialized hardware.
A possible solution to the problem of accommodating specific application requirements in processors is to use configurable processors having instruction sets and architectures which can be easily modified and extended to enhance the functionality of the processor and customize that functionality. Configurability allows the designer to specify whether or how much additional functionality is required for her product. The simplest sort of configurability is a binary choice: either a feature is present or absent. For example, a processor might be offered either with or without floating-point hardware. A highly advantageous system for developing, testing and implementing configurable processors is disclosed in United States patent application Ser. No. 09/246,047 to Killian et al.
There are several challenges which have largely prevented this method of improving application performance from becoming a mainstream design technique. The first challenge is in describing in a formal way the semantics of the new instructions. The Killian et al. application, for example, provided a specification language called the TIE™ (Tensilica Instruction Set-Extensions) language developed by Tensilica Corporation of Santa Clara, Calif. for defining new instructions; however, TIE is limited in the types of instructions which it can define. Specifically, TIE-defined instructions cannot access or modify any information stored in special registers, i.e., processor state, which significantly restricts the range of instructions obtainable and therefore limit the amount of performance improvement achievable.
Second, inventing new application-specific instructions involves complicated tradeoffs between cycle count reduction, additional hardware resources and CPU cycle-time impact. The third challenge is to obtain efficient hardware implementations for the new instructions without involving applications developers in the often tricky details of high-performance microprocessor implementations.
SUMMARY OF THE INVENTION
In view of the above problems of the prior art, it is an object of the present invention to provide a system and method for developing and implementing instruction set extensions which modify processor state.
It is another object of the present invention to provide a system and method for developing and implementing instruction set extensions that modify configurable processor registers.
These objects are achieved according to an aspect of the present invention by providing an automated processor design tool which uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. The standardized language is capable of handling instruction set extensions which modify processor state or use configurable processors. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.
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Clucas, R.; “Designing with a customisable microprocessor core,” Electronic Eng'g, vol. 71, No. 865, Feb. 1, 1999, p. 35.
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Compton et al., “Confgurable Computing: A Survey of Systems and Software,” Technical Report, Northwestern University, Dept. of ECE, 1999.
Hauck et al., “The Chimaera Reconfigurable Functional Unit.” Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 1997.
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Killian Earl A.
Ruddell Richard
Wang Albert Ren-Rui
Pillsbury & Winthrop LLP
set tion
Tensilica, Inc.
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