Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2001-03-07
2002-09-17
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S022000, C710S308000, C710S310000, C710S311000
Reexamination Certificate
active
06453368
ABSTRACT:
TECHNICAL FIELD
This invention relates to a data transfer method and a data transfer apparatus for transferring data between devices or memories respectively connected to two different buses, and more particularly to a data transfer method and a data transfer apparatus for carrying out diagnosis as to whether or not data transfer normally functions.
BACKGROUND ART
Hitherto, there has been known a system in which different buses such as main bus and sub bus are connected through a bus repeater such as gateway, etc. to carry out DMA transfer of data between these buses by DMA (Direct Memory Access) controller provided in the main bus.
For example, in the configuration as shown in
FIG. 1
, a main bus
101
and a sub bus
102
are both connected to a bus repeater
103
such as bus gateway, etc. A device
104
such as CPU or various interfaces, etc. and a DMA controller
105
are connected to the main bus
101
, and a device
106
and a memory
107
such as ROM, etc. are connected to the sub bus
102
.
In the example of
FIG. 1
, the DMA controller
105
on the main bus
101
also controls the sub bus
102
through the bus repeater
103
to thereby realize DMA transfer, e.g., between the device
104
and the device
106
. As stated above, if access times of respective buses are the same order even between different buses
101
,
102
, efficient data transfer can be carried out without useless wait (standby) time.
Meanwhile, in the case where different buses coexist within one system, there are many instances where bus widths and/or data access speeds are different. For example, in the example of
FIG. 1
, the main bus
101
has bus width of 32 bits and high data access speed and the sub bus
102
has bus width of 16 bits and low data access speed.
In the case where DMA transfer is caused to be carried out between buses in which bus widths and/or data access speeds are different, there is the drawback that useless wait (standby) time is caused to take place on the high speed bus, e.g., the main bus
101
of FIG.
1
.
In view of the above, it is conceivable to connect two different buses through buffer memory to carry out DMA transfer through this buffer memory, In this case, when attempt is made to carry out diagnosis as to whether or not DMA transfer normally functions, it is required to allow CPUs of respective buses to run in debugging mode. This is troublesome.
Moreover, in the case where data transfer has not been normally carried out, since it is considered that there is any defect in CPUs of both buses or diagnostic program, there are many instances where finding of the cause becomes very difficult.
Particularly, in the case where CPU or DMA controller, etc. is provided within one LSI, it takes long development time, and schedule of diagnosis, etc. becomes great problem.
Before LSI is designed or is tribally manufactured in practice, software simulation including peripheral equipment is carried out to confirm functions as much as possible. However, because it takes much time in simulation, sufficient verification cannot be carried out and there are actual circumstances where it is required to examine closely the problems in short time after tribally manufactured LSI, etc. is made up. Thus, there are many instances where difficulty of debugging as described above results in hindrance of development of product.
Further, in the case where data transfer is carried out between devices, there are arrangements of data convenient for respective devices. To cope with this, it is necessary to round down extra data, or to insert another data into the portion between data trains which have been transferred.
When CPU attempts to carry out an operation as described above with respect to data train developed on the memory, it once reads such data train into the register of the CPU thereafter to have to write it for a second time. For this reason, efficiency is very poor (low). This reduces the time required when CPU attempts to carry out other work, and is not therefore preferable.
Here, it is conceivable that DMA controller changes every time transfer source address or transfer destination address at the time of data transfer. In this case, address of transfer source and list of transfer quantity are prepared and DMA controller carries out DMA transfer in accordance with that list every time. However, CPU must prepare transfer specification table. As a result, there is the difficulty that overhead for checking transfer specification every time takes place, etc.
Moreover, in the case where different buses coexist within one system as described above, there are many instances where bus widths are different. For example, in the example of
FIG. 1
, the main bus
101
has bus width of 32 bits and high data access speed and the sub bus
102
has bus width of 16 bits and low data access speed. Also in the case where DMA transfer is caused to be carried out between buses where bus widths are different as stated above, there are instances where extra data is rounded down or another data is inserted into the portion between data trains which have been transferred. Also in this case, it is desirable that change of data structure or delimit of address can be carried out with ease.
DISCLOSURE OF THE INVENTION
This invention has been made in view of such actual circumstances, and its object is to provide a data transfer method and a data transfer apparatus which are capable of easily carrying out DMA transfer function between different two buses, and capable of specifying portion of the question in short time.
Moreover, another object of this invention is to provide a data transfer method and a data transfer apparatus which are capable of changing, in data transfer between different two buses, size of transfer data block with ease without giving burden on CPU, thus to realize improvement in the working efficiency.
Namely, in order to solve the above-described problems, this invention includes a first bus and a second bus, bus repeating means having buffer memory connected to both the first and second buses, first DMA (Direct Memory Access) control means connected to the first bus, and first data processing means (CPU) connected to the first bus, wherein the bus repeating means has a function to issue DMA request to the first DMA control means and a function to mask this DMA request by the first data processing means to mask the DMA request of the bus repeating means by the first data processing means to directly access the buffer memory within the bus repeating means.
In this case, it is mentioned that second DMA (Direct Memory Access) control means and second data processing means (CPU) are connected to the second bus, the first and second DMA control means carry out read/write operation of data with respect to buffer memory within the bus repeating means to thereby carry out data transfer between the first and second buses, the bus repeating means has a function to issue DMA request to the second DMA control means and a function to mask this DMA request by the second data processing means to mask DMA request of the bus repeating means by the second data processing means to directly access the buffer memory within the bus repeating means.
In this case, it is mentioned that DMA request on the other bus in the bus repeater is masked by one of the first and second data processing means (CPUs) to access the buffer memory within the bus repeater from on the other bus.
Moreover, this invention is characterized in that first and second buses different from each other are connected through bus repeating means having a buffer memory, first DMA (Direct Memory Access) control means is connected to the first bus, and second DMA control means is connected to the second bus to carry out DMA transfer between memory or device connected to the first bus and memory or device connected to the second bus through the buffer memory by these first and second DMA control means, and to mask, by data processing means (CPU), DMA request to the first or second DMA control means from the bus repeating means to directly access t
Fulwider Patton Lee & Utecht LLP
Gaffin Jeffrey
Park Ilwoo
Sony Computer Entertainment Inc.
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