Adder for reducing carry processing

Details Adder for reducing carry processing Adder for reducing carry processing

1992-06-24

1994-03-29

Malzahn, David H.

Boots, shoes, and leggings

364768, G06F 750

Patent

active

052991458

ABSTRACT:
An adder including a subdividing unit for subdividing an addend and an augend formed in plural bits into bit groups each having a specified number (an integer of 2 or larger) of bits, and an addition unit for executing parallel addition for each of the bit groups. The addition unit is arranged such that the addend and the augend are added together for each bit when they are represented in multivalued logic having three or more steps of logic values.

REFERENCES:
patent: 4620188 (1986-10-01), Sengchank
patent: 4866657 (1989-09-01), Shigeo et al.
patent: 4914614 (1990-04-01), Yamakawa
patent: 4979140 (1990-12-01), Darley
Morris, et al., "An Introduction to the Ternary Code Number System" Electronic Engineering Sep. 60 pp. 554-557.

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