Adder circuits and magnitude comparator

Details Adder circuits and magnitude comparator Adder circuits and magnitude comparator

1994-10-31

1996-07-23

Westin, Edward P.

Electronic digital logic circuitry

Exclusive function

Half-adder or quarter-adder

364768, 3401462, G05B 100

Patent

active

055393322

ABSTRACT:
An evaluation tree circuit is disclosed that produces a generate, a propagate, and a zero output for use in carry lookahead adders. Another evaluation tree circuit is disclosed that merges the generate, propagate, and zero signals from several adjacent bits or groups of bits. These evaluation trees may be used in self-resetting CMOS or CVSL circuits. They can be used to reduce the number of levels of logic in a carry lookahead adder. They can also be used to form a magnitude comparator, which is also disclosed.

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