Adder-based base cell for field programmable gate arrays

Details Adder-based base cell for field programmable gate arrays Adder-based base cell for field programmable gate arrays

1995-01-05

1996-01-30

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

326 39, 326 41, 326 53, 364768, H03K 19173, H03K 19177

Patent

active

054883156

ABSTRACT:
An adder-based base cell (10) is provided for field programmable gate arrays. The base cell (10) includes a first inverter (13) operable to receive a first input signal (A). A first NAND gate (12) is coupled to the first inverter (13) and is operable to receive a second input signal (B). A first 2:1 multiplexer (14) is coupled to the first NAND gate (12) and is operable to receive a third input signal (C). The output of the first 2:1 multiplexer (14) represents a first function (F1). A second inverter (17) is operable to receive a fourth input signal (D). A second NAND gate (16) is coupled to the second inverter (17) and is operable to receive a fifth input signal (E). An XOR gate (18) is coupled to the second NAND gate (16), is operable to receive a sixth input signal (F), and is coupled to the first 2:1 multiplexer (14). The output of the XOR gate represents a partial sum function (PS.sub.-- 1). A second 2:1 multiplexer (19) is operable to receive a seventh input signal (G), is operable to receive an eighth input signal (H) and is coupled to the XOR gate (18). The output of the second 2:1 multiplexer (19) represents a second function (F2).

REFERENCES:
patent: 4878192 (1989-10-01), Nishiyama et al.
patent: 5122685 (1992-06-01), Chan et al.
patent: 5338983 (1994-08-01), Agarwala
patent: 5424655 (1995-06-01), Chua

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