Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed
Reexamination Certificate
2001-03-15
2002-07-23
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
Optical characteristic sensed
C716S030000
Reexamination Certificate
active
06423557
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the manufacture of high performance semiconductor devices. More specifically, this invention relates to the inspection of a semiconductor wafer using scanning tools to find defects that occur during the manufacturing process. Even more specifically, this invention relates to the automatic classification, automatic selection of defects that require further analysis, the automatic selection of the equipment to perform the further analysis and the in-situ performance of the further analysis.
2. Discussion of the Related Art
In order to remain competitive, a semiconductor manufacturer must continuously increase the performance of the semiconductor integrated circuits being manufactured and at the same time, reduce the cost of the semiconductor integrated circuits. Part of the increase in performance and the reduction in cost of the semiconductor integrated circuits is accomplished by shrinking the device dimensions and by increasing the number of circuits per unit area on an integrated circuit chip. Another part of reducing the cost of a semiconductor chip is to increase the yield. As is known in the semiconductor manufacturing art, the yield of chips (also known as die) from each wafer is not 100% because of defects during the manufacturing process. The number of good chips obtained from a wafer determines the yield. As can be appreciated, a chip that must be discarded because of a defect increases the cost of the remaining usable chips.
A single semiconductor chip can require numerous process steps such as oxidation, etching, metallization and wet chemical cleaning. Some of these process steps involve placing the wafer on which the semiconductor chips are being manufactured into different tools during the manufacturing process. The optimization of each of these process steps requires an understanding of a variety of chemical reactions and physical processes in order to produce high performance, high yield circuits. The ability to view and characterize the surface and interface layers of a semiconductor chip in terms of their morphology, chemical composition and distribution is an invaluable aid to those involved in research and development, process, problem solving, and failure analysis of integrated circuits. A major part of the analysis process is to determine if defects are caused by one of the process tools, and if so, which tool caused the defects.
As the wafer is placed into different tools during manufacture, each of the tools can produce different types of particles that drop onto the wafer and cause defects that have the potential to decrease the yield. In order to develop high yield semiconductor processes and to improve existing ones, it is important to identify the sources of the various particles that cause defects and then to prevent the tools from dropping these particles onto the wafer while the wafers are in the tools.
In order to be able to quickly resolve process or equipment issues in the manufacture of semiconductor products, a great deal of time, effort and money is being expended by semiconductor manufacturers to capture and classify silicon based defects. Once a defect is caught and properly described and classified, work can begin to resolve the cause of the defect and to eliminate the cause of the defect. The biggest problem facing the semiconductor manufacturers and the most difficult problem to solve is the training and maintenance of a cadre of calibrated human inspectors who can classify all defects consistently and without error. Because of human inconsistency, Automatic Defect Classification (ADC) systems were developed.
One such system for automatically classifying defects consists of the following methodological sequence: (a) gather a defect image from a review station; (b) view the defect image and assign values to elemental descriptor terms called predicates that are general descriptors such as roundness, brightness, color, hue, graininess, etc.; and (c) assign a classification code to the defect based upon the values of all the predicates. A typical ADC system can have 40 or more quantifiable qualities and properties that can be predicates. Each predicate can have a specified range of values and a typical predicate can have a value assigned to it between 1 and 256. A value of 1 indicates that none of the value is present and a value of 256 indicates that the quality represented by the predicate is ideal. For example, a straight line would have a value of 1 for the predicate indicating roundness, whereas a perfect circle would have a value of 256 for the same predicate. The classification code for each defect is determined by the system from the combination of all the predicate values assigned to the defect. The goal of the ADC system is to be able to uniquely describe all the defect types, in such a manner that a single classification code can be assigned to a defect that has been differentiated from all other defect types. This is accomplished by a system administrator who trains an artificial intelligence system to recognize various combinations and permutations of the 40 or more predicates to assign the same classification code to the same type of defect. This would result in a highly significant statistical confidence in the probability that the defect, and all other defects of the same type or class, will always be assigned the same classification code by the ADC system.
The ADC system has been going through a continuous development cycle and is gaining more and more acceptance as a relative stable proven technology and useful tool for automatically generating “insightful” information on defects captured in modern semiconductor manufacturing operations. The ADC technology can be ported to SEM and other analysis tools. These analysis tools have added capabilities beyond generating an image, and include the ability to generate a chemical spectrum of a selected material by an electron dispersal analysis (EDX), the ability to cut a hole at a selected site for cross-sectional review by fixed ion beam (FIB), the ability to cut and remove a slice of material for extremely high resolution imaging by transmission electron microscopy (TEM). If these analytical techniques could be coupled with the automatic capability of automatic defect classification (ADC), it would aid tremendously in finding root causes of defects in a product line.
Therefore, what is needed is a method of coupling the automatic defect classification capabilities with the capabilities of various analysis tools for automatic elemental analysis of a given defect of interest.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other objects and advantages are obtained by a method of scanning a semiconductor wafer for defects that occur during the manufacturing process and automatically selecting defects for destructive and non-destructive testing.
In accordance with a first aspect of the invention, an inspection wafer is scanned for defect information, which is sent to a defect management system that selects defects to analyze in an automatic defect classification operation.
In accordance with another aspect of the invention, the automatic defect classification operation selects defects for further analysis, determines what type of analysis is required for the defects selected for further analysis and selects the equipment for the required further analysis. The automatic defect classification selects equipment from the following: fixed ion beam equipment, transmission electron microscopy equipment, electron dispersal analysis equipment, scanning electron microscopy equipment and Rutherford back scattering equipment.
In accordance with another aspect of the invention, the automatic defect classification operation causes the required further analysis to be performed in situ.
The described invention thus provides a method of automatically performing required destructive and non-destructive analysis in-situ during the manufacture of a semiconductor wafer.
The present i
Steffan Paul J.
Yu Allen S.
Advanced Micro Devices , Inc.
Chaudhuri Olik
Nelson H. Donald
Thompson Craig
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