Adaptively reducing memory latency in a system

Details Adaptively reducing memory latency in a system Adaptively reducing memory latency in a system

2006-09-25

2010-06-01

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711SE12021

Reexamination Certificate

active

07730264

ABSTRACT:
In one embodiment, the present invention includes a method for routing an early request for requested data on a bypass path around a transaction processing path of a first agent if the requested data is not present in a cache memory of the first agent, and opportunistically transmitting the early request from the first agent to a second agent based on load conditions of an interconnect between the first agent and the second agent. In this way, reduced memory latencies may be realized. Other embodiments are described and claimed.

REFERENCES:
patent: 6009488 (1999-12-01), Kavipurapu
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patent: 7320022 (2008-01-01), Hayter et al.
patent: 2003/0140202 (2003-07-01), LaBerge
patent: 2004/0148472 (2004-07-01), Barroso et al.
patent: 2005/0050278 (2005-03-01), Meier et al.
U.S. Appl. No. 11/392,335, filed Mar. 29, 2006, entitled “Speculatively Performing Read Transactions” by Ling Cen, Vishal Moondhra and Tessil Thomas.

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