Adaptive writeback of cache line data in a computer operated wit

Details Adaptive writeback of cache line data in a computer operated wit Adaptive writeback of cache line data in a computer operated wit

1998-10-21

2000-10-03

Nguyen, Hiep T.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711133, 711140, 711144, 711145, 710 35, G06F 1208

Patent

active

061287075

ABSTRACT:
System and method for selectively adapting the burst mode writeback from cache to main memory consistent with the extent of a cache line actually modified by the processor and at the granularity of the bus connecting the cache to main memory. A cache controller speculatively reads a cache line with each address issued by this processor. When the address is related to a read cycle of the processor, the data is forwarded to the processor. When the address is related to a write cycle of the processor, the data read from the cache is compared to the write data from the processor to detect changes at a granularity consist with the size of the system data bus. The cache line stored in the cache upon such writing is marked at the granularity of the system data bus with tag bits to indicate which portions have been modified. Upon deallocation, the tag bits stored in the cache directory identify those portions of the cache lines requiring transmission back to main memory as an aspect of the burst writeback operation.

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