Adaptive threshold voltage CMOS circuits

Details Adaptive threshold voltage CMOS circuits Adaptive threshold voltage CMOS circuits

1995-10-12

1997-05-13

Westin, Edward P.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326 17, 326 83, H03K 190948, H03K 19017

Patent

active

056296380

ABSTRACT:
A CMOS circuit in which the threshold voltage of at least one MOS transistor of the CMOS circuit is altered is disclosed. By altering the threshold voltage the speed/power dissipation tradeoff can be modified to match the design criteria of a particular CMOS circuit. For example, to increase the pull-up speed of the PMOS transistor in the CMOS transistor pair of a CMOS circuit, the threshold voltage of selective MOS transistors is lowered. The altering can occur on a device level or a circuit level. A method for designing such CMOS logic circuits is also disclosed.

REFERENCES:
patent: 4250406 (1981-02-01), Alaspa
patent: 4463273 (1984-07-01), Dingwall et al.
patent: 4489246 (1984-12-01), Nishiuchi
patent: 4558234 (1985-12-01), Suzuki et al.
patent: 4595845 (1986-06-01), Briggs
patent: 4612461 (1986-09-01), Sood
patent: 4808854 (1989-02-01), Reinagel
patent: 4956691 (1990-09-01), Culley et al.
patent: 5017811 (1991-05-01), Worley
patent: 5034628 (1991-07-01), Matsuzawa et al.
patent: 5057715 (1991-10-01), Larsen et al.
patent: 5132567 (1992-07-01), Puri et al.
patent: 5150186 (1992-09-01), Pinney et al.
patent: 5200921 (1993-04-01), Okajima
"Threshold-Controlled CMOS-Chips for Low-Power Low-Voltage Applications", IBM Technical Disclosure Bulletin, vol. 36, No. 1, Jan. 1993, pp. 345-347.
"Asymmetric CMOS Logic Gates", IBM Technical Disclosure Bulletin, vol. 32, No. 2, Jul. 1989, pp. 421-422.
Cherkauer, Brian S., and Friedman, Eby G., "The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs", IEEE International Symposium on Circuits and Systems, vol. 3, May 1993, pp. 2110-2113.
Oyamatsu et al., "Design Methodology of Deep Submicron CMOS Devices for 1V Operation", 1993 Symposium on VLSI Technology, pp. 89-90.
Kitsukawa et al., "WP 3.4: 256Mb DRAM Technologies for File Applications", ISSCC 93/Session3/Non-Volatile, Dynamic, and Experimental Memories/Paper WP 3.4, 1993 IEEE International Solid State Circuits Conference, pp. 48-49.
Shimohigashi et al., "Low Voltage ULSI Design--The Lower, The Better--", 1992 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 4-6, 1992, Seattle Washington, pp. 54-58.
Martin Gold, "IEEE confab eyes 2-V future", Electronic Engineering Times, Oct. 11, 1993, p. 16.

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