Adaptive thread ID cache mechanism for autonomic performance...

Details Adaptive thread ID cache mechanism for autonomic performance... Adaptive thread ID cache mechanism for autonomic performance...

2007-11-27

2007-11-27

Shah, Sanjiv (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S128000, C711S133000, C711S134000, C711S214000, C711S220000

Reexamination Certificate

active

10670717

ABSTRACT:
An apparatus and method for inhibiting data cache thrashing in a multi-threading execution mode through simulating a higher level of associativity in a data cache. The apparatus temporarily splits a data cache into multiple regions and each region is selected according to a thread ID indicator in an instruction register. The data cache is split when the apparatus is in the multi-threading execution mode indicated by an enable cache split bit.

REFERENCES:
patent: 6874056 (2005-03-01), Dwyer et al.
patent: 2006/0195683 (2006-08-01), Kissell

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