Adaptive segmentation of shared cache

Details Adaptive segmentation of shared cache Adaptive segmentation of shared cache

2005-12-06

2005-12-06

Nguyen, T (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S170000, C711S171000, C711S172000, C711S173000

Reexamination Certificate

active

06973538

ABSTRACT:
A system, method and computer readable medium are provided for segmenting a cache that is shared by multiple processors. According to the method, a first segment of the cache is allocated to a first processor and a second segment of the cache is allocated to a second processor. An execution time of at least one task on the first processor is monitored. If the execution time of the at least one task is greater than an allowed execution time minus a predetermined margin, the size of the first segment of the cache that is allocated to the first processor is increased. In one preferred method, if the execution time of the at least one task is significantly less than the allowed execution time minus the predetermined margin, the size of the first segment of the cache that is allocated to the first processor is decreased.

REFERENCES:
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patent: 5737747 (1998-04-01), Vishlitzky et al.
patent: 6226608 (2001-05-01), Fielder et al.
patent: 6647477 (2003-11-01), Janoska et al.
patent: 2002/0065992 (2002-05-01), Chauvel et al.

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