Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Patent
1994-09-20
1996-03-12
Westin, Edward P.
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
327525, 34082584, 364489, 364490, H03K 19177, H01H 3776
Patent
active
054989795
ABSTRACT:
For antifuse programmable integrated circuit devices, in particular FPGA devices, the invention allows for alternative routing around antifuses which fail to program. The chip architecture includes wiring segments and antifuses which together allow for alternative routes around every antifuse in the event of failure of that antifuse. The method includes programming the device under control of a computer which can recalculate routes in the event of an antifuse which fails to program. Preferably the initial routing distributes unused wiring segments through the chip to be available for routing around a failed antifuse. When a failure occurs, the method includes determining an alternative route around every failed antifuse. The alternative route may be established directly after the antifuse has failed or after all initially selected antifuses have been programmed. The method also includes swapping of logic cell inputs, logic cells, and/or logic blocks from their original layout to adapt to a failed antifuse without changing the timing of signals which would have used the failed antifuse.
REFERENCES:
patent: 4605928 (1986-08-01), Georgiou
patent: 4758745 (1988-07-01), Elgamal et al.
patent: 4974048 (1990-11-01), Chakravorty et al.
patent: 5153463 (1992-10-01), Keiichi
patent: 5223792 (1993-06-01), El-Ayat et al.
patent: 5349248 (1994-09-01), Parlour et al.
Soukup, J.; "Circuit Layout"; IEEE, vol. 69; Oct. 1981; pp. 1281-1304; (article pp. 21-44).
Greene, J.; Roychowdhury, V.; Kaptanoglu, S.; El Gamal, A.; "Segmented Channel Routing"; Actel Corporation; 27th ACM/IEEE Design Automated Conference; 1990; Paper 34.2; pp. 567-572.
Brown, S.; Rose, J.; Vranesic, Z.; "A Detailed Router for Field-Programmable Gate Arrays", IEEE International Conference on Computer-Aided Design, ICCAD-90, Digest of Technical Papers, Nov. 11-15, 1990; pp. 382-385.
Lorenzetti, M.; Baeder, D.; "Physical Design Automation of VLSI Systems"; Chapter 5 `Routing`; Edited by Bryan Preas and Michael Lorenzetti; The Benjamin/Cummings Published Company, Inc.; copyright 1988; pp. 157-210.
Goetting F. Erich
Parlour David B.
Trimberger Stephen M.
Young Edel M.
Harms Jeanette S.
Santamauro Jon
Westin Edward P.
Xilinx , Inc.
Young Edel M.
LandOfFree
Adaptive programming method for antifuse technology does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Adaptive programming method for antifuse technology, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Adaptive programming method for antifuse technology will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2103246