Adaptive programming method and apparatus for flash memory...

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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Reexamination Certificate




1. Field of the Invention
The present invention relates to the field of analog signal storage.
2. Prior Art
Existing multi-level analog non-volatile flash memory storage solutions use a long sequence of programming pulses to program the flash memory cells. Each successive pulse has a slightly higher voltage than the last (like a voltage staircase). After each programming pulse, the state of the flash memory cell is measured and compared to the input voltage Depending on the result of the comparison, another program pulse will be generated or the programming will stop. Such a system has to use at least the same number of pulses as the desired number of levels to be stored in the memory cell. For example, to program a cell to the 256
level will require at least 256 pulses. In order to achieve the required system speed, multiple cells have to be programmed in parallel. This requires a large number of circuits, one for each cell. These circuits and their supporting circuits consume a significant amount of area and power.
For analog signal recording and playback utilizing nonvolatile memory integrated circuits, as described in U.S. Pat. No. 5,220,531 by Trevor Blyth and Richard Simko, EEPROM (electrically erasable programmable read only memory) cells are used. The programming pulse is divided into a series of coarse pulses and a series of fine pulses to reduce the total number of pulses required. This method still requires a large number of pulses and many cells have to be programmed in parallel.
Another solution is U.S. Pat. No. 5,959,883 by Peter Holzmann, et al. entitled “Recording and Playback Integrated System for Analog Non-volatile Flash Memory.” This method also uses coarse and fine pulses, and still requires many pulses and many cells to be programmed in parallel.
In U.S. Pat. No. 5,963,462 by Larry Engh, et al. “Integrated Circuit System for Analog Signal Storing and Recovery Incorporating Read While Writing Voltage Program Method” (1999), a method is described to program a single cell using “read-while-writing” operations. This requires only two or three pulses, but the method applies to EEPROM memory and cannot be applied to flash memory.
Adaptive programming method and apparatus for flash memory analog storage. The present invention method is to adjust the voltage of the programming pulse each time based on the result of the previous pulse. The expected change in the programmed value is compared to the measured change, and the difference used to improve the model of that cell after each programming pulse. The algorithm is “adaptive” because the voltage of each pulse is adapted to whatever the cell needs. If the cell is programming too slowly, the voltage is increased dramatically to make it faster. Conversely if the results show that a particular cell is programming too fast, the next voltage pulse is increased by only a small amount (or even decreased if necessary). Because the response of the cell is non-linear, a special analog circuit is used to calculate the optimum voltage for each pulse. As one alternative, a digital calculation may also be used to program the cells. Because of the programming speed of the exemplary method, a voice signal may be sampled and stored in flash memory one cell at a time. Variable programming parameters other than voltage may be used if desired.

patent: 5220531 (1993-06-01), Blyth et al.
patent: 5623436 (1997-04-01), Sowards et al.
patent: 5629890 (1997-05-01), Engh
patent: 5754470 (1998-05-01), Engh et al.
patent: 5877984 (1999-03-01), Engh
patent: 5926409 (1999-07-01), Engh et al.
patent: 5959883 (1999-09-01), Brennan et al.
patent: 5963462 (1999-10-01), Engh et al.
patent: 6040993 (2000-03-01), Chen et al.
patent: 6046934 (2000-04-01), Lin
patent: 6134141 (2000-10-01), Wonh
patent: 6175937 (2001-01-01), Norman et al.


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