Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-09-28
2003-09-16
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06622294
ABSTRACT:
FIELD
The invention relates to integrated circuit layout. More particularly, the invention relates to area-efficient techniques for placing and routing signal nets and power and ground supply lines in an integrated device layout to control electrical cross-coupling between adjacent signal lines.
BACKGROUND
As processes for manufacturing integrated devices allow minimum line sizes to decrease, the potential for interconnect noise due to switching cross-coupling capacitance increases. This switching cross-coupling capacitance increases the difficulty of converging high performance circuits by widening the transition windows of signals to account for unpredictable transition states of neighboring signals, as well as by causing failures. Convergence refers to conditions under which all timing requirements are met.
In view of this situation, designers often attempt to reduce switching cross-coupling capacitance by shielding sensitive signal nets using power supply (Vcc) or ground (Vss) lines. The set of lines providing any combination of a positive supply voltage, a negative supply voltage and/or ground are referred to herein as “power lines.” Shielding can be accomplished by placing sensitive signal nets adjacent to pre-existing power lines or by adding power lines adjacent to the sensitive signal lines for the purpose of shielding.
With the effects of switching cross-coupling capacitance increasing with each generation of integrated device manufacturing processes, the proportion of signals requiring shielding, and consequently the area used by the shields also increases. Because design blocks layouts are often wire-limited, an increase in the number of power lines required solely for shielding increases the die area required to manufacture the integrated device.
Furthermore, detailed shielding requirements are available only at late stages in the design process, at which time the die area available to lay out each converged design block may already have been allocated. In such a scenario, if the layout of a converged design block cannot be carried out in its planned area, extensive delays can be incurred due to redesign of the surrounding design blocks.
L. He, “Simultaneous Shield Insertion and Net Ordering for Capacitive and Inductive Coupling Minimization,” Proc. ISPD'00 (hereinafter “the He Paper”) discloses a technique for integrated shielding and signal net ordering. However, the He Paper focuses on signal net ordering and shield insertion primarily for inductive noise under a simplistic model and is not well suited to layouts containing may prerouted signal nets and shields, which is common. Furthermore, the He Paper does not address either shield sharing or power grid perturbation.
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Gupta Satyanarayan
Saxena Prashant
Blakely , Sokoloff, Taylor & Zafman LLP
Kik Phallaka
Smith Matthew
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