Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation
Reexamination Certificate
2011-08-16
2011-08-16
Kinkead, Arnold (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Tuning compensation
C331S00100A, C331S00100A, C331S017000, C331S034000, C331S03600C, C331S17700V, C331S17700V, C375S376000
Reexamination Certificate
active
07999622
ABSTRACT:
An embodiment of the invention is a circuit for adaptive phase noise cancellation for a fractional-N PLL. A preferred embodiment employs a split loop filter architecture. Two loop filter halves separately drive half-sized parallel varactors in a voltage controlled oscillator (VCO) and also drive a differential-input lowpass frequency selective circuit, e.g., a differential-input integrator in a least mean squared (LMS) feedback loop. The output of the differential-input lowpass frequency selective circuit controls the gain matching of a phase noise cancellation path to minimize phase noise arising from quantization error associated with the sequence of divider modulus values in the fractional-N PLL. The two varactor capacitances add together in the VCO tank, so the VCO frequency depends on the common-mode loop filter voltage and is relatively insensitive to differential-mode voltage. In contrast, the differential integrator operates on the differential-mode voltage from the two loop filter halves but attenuates their common-mode voltage.
REFERENCES:
patent: 6011822 (2000-01-01), Dreyer
patent: 6903585 (2005-06-01), Keaveney
patent: 7148758 (2006-12-01), Ross et al.
patent: 7439783 (2008-10-01), Weller et al.
patent: 2004/0066244 (2004-04-01), Takinami et al.
patent: 2005/0090218 (2005-04-01), Ishida et al.
patent: 2005/0185746 (2005-08-01), Jung
patent: 2008/0258949 (2008-10-01), Galton
patent: 2009/0039929 (2009-02-01), Kossel
J. Craninckx and M. Steyaert. “A Fully Integrated CMOS DCS-1800 Frequency Synthesizer,”IEEE Journal of Solid-State Circuits, vol. 33, No. 12, Dec. 1998.
A. Fishov, E. Siragusa, J. Welz, E. Fogleman and I. Galton. “Segmented Mismatch Shaping D/A Conversion.”Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 4, pp. 679-682, May 2002.
M. Gupta and B-S Song. “A 1.8GHz Spur-Cancelled Fractional-N Frequency Synthesizer with LMS-Based DAC Gain Calibration,”Digest of the 2006 International Solid-State CircuitsConference, Feb. 2006.
P. Larsson. “A 2-1600 MHz CMOS Clock Recovery PLL with Low-Vdd Capability,”IEEE Journal of Solid-State Circuits, vol. 34, No. 12, Dec. 1999.
J. Lee, S-O Lee, M. Yoh, I. Ryu and B-H Park. “A 13mW 2GHz/520MHz Dual-Band Frequency Synthesizer for PCS Applications,”Journal of the Korean Physical Society, vol. 39, No. 1, Jul. 2001.
S. T. Lee, S. J. Fang, D. J. Allstot, A. Bellaouar, A. R. Fridi, and P. A. Fontaine. “A Quad-Band GSM-GPRS Transmitter with Digital Auto-calibration,”IEEE Journal of Solid-State Circuits, vol. 39, No. 12, Dec. 2004.
F. L. Martin. “A Wideband 1.3GHz PLL for Transmit Remodulation Suppression,” IEEEInternational Solid-State Circuits Conference, vol. 44, Feb. 2001.
S. E. Meninger and M. H. Perrott. “A Dual Band 1.8GHz/900MHz 750kb/s GMSK Transmitter Utilizing a Hybrid PFD/DAC Structure for Reduced Broadband Phase Noise,”2005 Symposium on VLSI Circuits, Jun. 2005.
S. Pamarti, L. Jansson and I. Galton. “A Wideband 2.4GHz Delta-Sigma Fractional-N PLL with 1Mb/s In-Loop Modulation,”IEEE Journal of Solid-State Circuits, vol. 39, No. 1, Jan. 2004.
S. Pamarti and I. Galton. “Phase-Noise Cancellation Design Tradeoffs in Delta-Sigma Fractional-N PLLs,”IEEE Transactions on Circuits and Systems II : Analog and Digital Signal Processing, vol. 50, No. 11, Nov. 2003.
M. H. Perrott, M. D. Trott and C. G. Sodini. “A Modeling Approach for SD Fractional-NFrequency Synthesizers Allowing Straightforward Noise Analysis,”IEEE Journal of Solid-State Circuits, vol. 37, No. 8, Aug. 2002.
K. Shu, E. Sanchez-Sincencio, J. Silva-Martinez and S. H. K. Embabi. “A 2.4-GHz Monolithic Fractional-N Frequency Synthesizer with Robust Phase-Switching Prescaler and Loop Capacitance Multiplier,”IEEE Journal of Solid-State Circuits, vol. 38, No. 6, Jun. 2003.
A. Sripad and D. Snyder. “A Necessary and Sufficient Condition for Quantization Errors to be Uniform and White,”IEEE Transactions on Acoustics, Speech and Signal Processing, vol. 25, No. 5, Oct. 1977.
E. Temporiti, G. Albasini, I. Bietti, R. Castello and M. Colombo. “A 700-kHz bandwidth Sigma-Delta Fractional Synthesizer with Spurs Compensation and Linearization Techniques for WCDMA Applications,”IEEE Journal of Solid-State Circuits, vol. 39, No. 9, Sep. 2004.
M. Zargari, M. Terrovitis, S-H Jen, B. J. Kaczynski, L. Meelan, M. P. Mack, S. S. Mehta, S. Mendis, K. Onodera, H. Samavati, W. W. Si, K. Singh, A. Tabatabaei, D. Weber, D. K. Su and B. A. Wooley. “A Single-Chip Dual-Band Tri-Mode CMOS Transceiver for IEEE 802.11a/b/g Wireless LAN,”IEEE Journal of Solid-State Circuits, vol. 39, No. 12, Dec. 2004.
Galton Ian
Swaminathan Ashok
Greer Burns & Crain Ltd.
Kinkead Arnold
Tan Richard
The Regents of the University of California
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