Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2003-12-30
2008-10-07
Peugh, Brian R (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S150000
Reexamination Certificate
active
07433993
ABSTRACT:
In a memory system having multiple erase blocks in multiple planes, a selected number of erase blocks are programmed together as an adaptive metablock. The number of erase blocks in an adaptive metablock is chosen according to the data to be programmed. Logical address space is divided into logical groups, a logical group having the same size as one erase block. Adaptive logical blocks are formed from logical groups. One adaptive logical block is stored in one adaptive metablock.
REFERENCES:
patent: 5043940 (1991-08-01), Harari
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5095344 (1992-03-01), Harrari
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5315541 (1994-05-01), Harari et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5367484 (1994-11-01), Alexander et al.
patent: 5404485 (1995-04-01), Ban
patent: 5473765 (1995-12-01), Gibbons et al.
patent: 5532962 (1996-07-01), Auclair et al.
patent: 5570315 (1996-10-01), Tanaka et al.
patent: 5661053 (1997-08-01), Yuan
patent: 5742934 (1998-04-01), Shinohara et al.
patent: 5751634 (1998-05-01), Itoh
patent: 5768192 (1998-06-01), Eitan
patent: 5774397 (1998-06-01), Endoh et al.
patent: 5798968 (1998-08-01), Lee et al.
patent: 5860124 (1999-01-01), Matthews et al.
patent: 5890192 (1999-03-01), Lee et al.
patent: 5903495 (1999-05-01), Takeuchi et al.
patent: 5907856 (1999-05-01), Estakhri et al.
patent: 5909449 (1999-06-01), So et al.
patent: 5930167 (1999-07-01), Lee et al.
patent: 5937425 (1999-08-01), Ban
patent: 6011725 (2000-01-01), Eitan
patent: 6034897 (2000-03-01), Estakhri et al.
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6125435 (2000-09-01), Estakhri et al.
patent: 6141249 (2000-10-01), Estakhri et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6226728 (2001-05-01), See et al.
patent: 6272610 (2001-08-01), Katayama et al.
patent: 6304980 (2001-10-01), Beardsley et al.
patent: 6377500 (2002-04-01), Fujimoto et al.
patent: 6401160 (2002-06-01), See et al.
patent: 6421279 (2002-07-01), Tobita et al.
patent: 6426893 (2002-07-01), Conley et al.
patent: 6456528 (2002-09-01), Chen
patent: 6490649 (2002-12-01), Sinclair
patent: 6522580 (2003-02-01), Chen et al.
patent: 6542956 (2003-04-01), Lee et al.
patent: 6563734 (2003-05-01), Taki
patent: 6567307 (2003-05-01), Estakhri
patent: 6571261 (2003-05-01), Wang-Knop et al.
patent: 6591330 (2003-07-01), Lasser
patent: 6643170 (2003-11-01), Huang et al.
patent: 6725321 (2004-04-01), Sinclair et al.
patent: 6763424 (2004-07-01), Conley
patent: 6871259 (2005-03-01), Hagiwara et al.
patent: 6898662 (2005-05-01), Gorobets
patent: 6988175 (2006-01-01), Lasser
patent: 7032065 (2006-04-01), Gonzalez et al.
patent: 2001/0042882 (2001-11-01), Chang et al.
patent: 2002/0099904 (2002-07-01), Conley
patent: 2003/0053334 (2003-03-01), Chen
patent: 2003/0065899 (2003-04-01), Gorobets
patent: 2003/0076709 (2003-04-01), Huang et al.
patent: 2003/0109093 (2003-06-01), Harari et al.
patent: 2003/0110343 (2003-06-01), Hagiwara et al.
patent: 2004/0030825 (2004-02-01), Otake et al.
patent: 2004/0103241 (2004-05-01), Chang et al.
patent: 2005/0141312 (2005-06-01), Sinclair et al.
patent: 2005/0141313 (2005-06-01), Gorobets et al.
patent: 2005/0144358 (2005-06-01), Conley et al.
patent: 2005/0144360 (2005-06-01), Bennet et al.
patent: 2005/0144363 (2005-06-01), Sinclair
patent: 2005/0144365 (2005-06-01), Gorobets et al.
patent: 2005/0144367 (2005-06-01), Sinclair
patent: 2005/0166087 (2005-07-01), Gorobets
patent: 0 887 732 (1998-12-01), None
patent: 0 977 121 (2000-02-01), None
patent: 1424631 (2004-06-01), None
patent: 5314019 (1993-11-01), None
patent: WO 00/49488 (2000-08-01), None
patent: WO 01/18640 (2001-03-01), None
patent: WO 02/058074 (2002-07-01), None
patent: WO 03/027828 (2003-04-01), None
patent: WO 03/029951 (2003-04-01), None
patent: WO 2004/040457 (2004-05-01), None
patent: WO 2004/040458 (2004-05-01), None
patent: WO 2004/040459 (2004-05-01), None
patent: WO 2004/040578 (2004-05-01), None
Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEE Electron Device Letters, vol. 21, No. 1, Nov. 2000, pp. 543-545.
EPO/ISA, “Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration”, mailed in related PCT/US2004/043692 on May 4, 2005, 9 pages.
ISA/EPO, “Communication Relating to the Results of the Partial International Search,” mailed in related PCT/US2004/043680 on Jul. 5, 2005, 3 pages.
Bennett et al., “Scratch Pad Block”, U.S. Appl. No. 11/016,285, filed Dec. 16, 2004, 55 pages.
Chang, Li-Pin et al., “An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems”, Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium, Sep. 24, 2002, pp. 187-196.
EPO/ISA, “Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration”, mailed in related PCT/US2004/043597 on Aug. 8, 2005, 12 pages.
EPO/ISA, “Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration”, mailed in related PCT/US2004/043680 on Sep. 23, 2005, 18 pages.
USPTO, “Office Action,” mailed in related U.S. Appl. No. 10/841,118 on Jun. 16, 2006, 29 pages.
USPTO, “Final Office Action,” mailed in related U.S. Appl. No. 10/841,118 on Feb. 6, 2007, 32 pages.
USPTO, “Notice of Allowance,” mailed in related U.S. Appl. No. 11/016,271 on Jun. 13, 2007, 16 pages.
European Patent Office, Examiner's Report mailed in corresponding European Application No. 04 815 389.4 on Aug. 23, 2007, 5 pages.
Kim et al., “A Space-Efficient Flash Translation Layer for CompactFlash Systems,” IEEE Transaction on Consumer Electronics, vol. 48, No. 2, May 2002, pp. 366-375.
USPTO, Office Action, mailed in related U.S. Appl. No. 10/841,118 on Oct. 19, 2007, 9 pages.
USPTO, “Notice of Allowance,” mailed in related U.S. Appl. No. 11/016,271 on Jan. 31, 2008 (13 pages).
SIPO issued “Office Action” in related Chinese Patent Application dated Dec. 7, 2007 (14 pages).
Peugh Brian R
San Disk Corportion
Weaver Austin Villeneuve & Sampson LLP
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