Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1997-12-29
2002-11-26
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C365S233100, C713S400000, C713S501000, C714S731000, C714S744000
Reexamination Certificate
active
06487647
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally pertains to signal timing for memory access and, more particularly, to adaptive memory interface timing generation.
2. Description of the Related Art
Computers typically include a number of interconnected, discrete components that communicate over “buses” and share a variety of system resources. One or more processors generally execute programmed instructions stored in memory and communicate with the outside world using a number of input/output (“I/O”) techniques. The processor usually breaks down the programmed tasks into subtasks and parcels the subtasks out to other components to perform. For instance, the processor may instruct an I/O controller to handle I/O functions and a memory controller to manage memory functions. Since more than one component uses the various buses and because these components frequently operate relatively independently of one another, the receipt and transmission of signals must be properly timed.
Signal timing is provided by one or more timing signals, or “clocks,” within the computer. A computer includes what might be called a “system clock,” which is an electrical signal oscillating at a particular frequency. Some computer components may need to operate at frequencies higher than that of the system clock and, so, some components have their own internal clock signals. Internal clocks typically have a frequency different from, and generally higher than, that of the system clock. Examples of such components include processors, such as microprocessors and digital signal processors (“DSPs”), and controllers, such as graphics and memory controllers.
Historically, system-wide timing constraints required all components to operate on the system level relative to the system clock to provide a common timing reference with which to coordinate their operation and use of system resources. For example, a processor might request a memory controller to provide certain information from memory over the data bus, which request requires both the processor and the memory controller each to perform several discrete actions. Both the processor and the memory controller have internal clocks operating independently of one another that are used to perform the discrete actions without regard to what is happening internally of the other component. The processor and the controller, however, both synchronize their internal clocks to the system clock. Thus, the processor can coordinate its receipt of the information transmitted by the memory controller over the data bus because the receipt and transmission are both performed relative to the system clock.
One disadvantage to this historical approach was that the processor essentially had to wait around to receive the requested data from the memory controller. The processor could not be sure when the memory controller would have the data ready and so would simply wait. Early on, this was not significant as memory outperformed processors in terms of speed. However, recent advances in processor design emphasize this disadvantage as processors operate at ever higher frequencies. The disadvantage is also exacerbated by the increasing amount of data that must be handled by processors and memory.
One technique addressing this disadvantage uses synchronous dynamic random access memory (“SDRAM”). The internal clock of the memory controller is directly synchronized to the internal clock of the processor and controls the operations of the SDRAM devices. More particularly, the SDRAM device is designed so that all operations are synchronized to a positive edge clock, i.e., upon when an input clock, which is nominally the memory controller internal clock, rises. The SDRAM is also designed to always perform read and write operations within a certain number of clock cycles. The processor consequently knows when the SDRAM and the memory controller will have the data ready for transmission and can perform other tasks in the meantime. In addition to being quicker, this technique also simplifies the control interface between the memory controller and the rest of the system and is less expensive to manufacture.
Thus, the SDRAM receives an external clock signal that times its operations. An SDRAM receives a command and accordingly stores data written to the SDRAM or outputs data read from the SDRAM within a certain number of cycles. For data to be written to or read from the SDRAM reliably, the data must be determinate for some period of time before the operation is performed. The period of time is called the “setup” time. Similarly, that data must be determinate for a period of time after the operation begins. This period of time is called the “hold” time. Implementations employing SDRAMs, and other types of synchronous memory devices, must observe setup and hold times to operate correctly.
Conventional SDRAM designs also have drawbacks. They statically use the same clock to time both the transmission and the receipt of data signals, thus forcing awkward board layouts to deal with common timing problems such as clock-to-out and flight time mismatches. They also fail to track operating characteristics such as temperature, voltage, and component specific variations. All of these characteristics affect component operation to some degree and, hence, the timing requirements for signals transmitted to and from the component.
Some conventional SDRAM designs employ line matching buffers to cope with some of these drawbacks by reducing board sensitivity. However, although SDRAMs receive timing on writes thereto, they do not send out timing on reads therefrom. Line matching buffers, while canceling out adverse factors affecting writes to the SDRAM, thererfore do not affect the reads therefrom. Thus, this technique does not compensate for the SDRAM itself.
To account for these effects, system designers typically provide greater tolerances in the timing scheme. System designers typically use what might be called “effective” setup and hold times. The effective setup and hold times are longer than are the actual setup and hold times required by the SDRAM. Thus, in the event there are any timing delays caused by such extraneous factors, the extra time will ensure the data is determinate for at least the actual setup and hold period.
This approach has been effective because of the increased performance available from SDRAMs. The SDRAMs were so efficient the design could afford a little extra margin in the setup and hold periods even in light of faster processor speeds. However, increasing demands for higher system performance require tighter timing controls to reduce delays in overall system operation. Thus, there consequently is a need for a new technique for timing data transmission to and from SDRAMs.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
The invention, in one embodiment, is a method of operating a synchronous memory device generally including providing a clock signal to the synchronous memory device to time the operation thereof and adapting the timing of at least one of reads from and writes to the synchronous memory device to improve timing parameters for the operation thereof.
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