Adaptive keeper sizing for dynamic circuits based on fused...

Details Adaptive keeper sizing for dynamic circuits based on fused... Adaptive keeper sizing for dynamic circuits based on fused...

2005-07-05

2005-07-05

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000

Reexamination Certificate

active

06914452

ABSTRACT:
An invention is provided for an adaptive keeper circuit. The adaptive keeper circuit includes a first keeper transistor having a first terminal in electrical communication with a power supply and a second terminal in electrical communication with an internal dynamic node. In addition, a second keeper transistor is included that is configured in parallel to the first keeper transistor. The second keeper transistor also has a first terminal in electrical communication with the power supply. The second keeper transistor can be added to the first keeper transistor using a feedback bit line, which is configured to control current flow between the second keeper transistor and the internal dynamic node based on a state of the feedback bit line. The state of the feedback bit line is based on a process corner characteristic of the die. Additional keeper transistors and corresponding feedback bit lines can be added to the keeper circuit to increase flexibility.

REFERENCES:
patent: 6002292 (1999-12-01), Allen et al.
patent: 6404235 (2002-06-01), Nowka et al.
patent: 6466056 (2002-10-01), Greener
patent: 6549040 (2003-04-01), Alvandpour et al.
patent: 6690604 (2004-02-01), Hsu et al.

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