Electrical computers and digital data processing systems: input/ – Interrupt processing – Programmable interrupt processing
Reexamination Certificate
2006-07-18
2008-10-28
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
Programmable interrupt processing
C710S263000
Reexamination Certificate
active
07444451
ABSTRACT:
The present invention relates to an adaptive interrupts coalescing system with recognizing minimum delay packets. The adaptive interrupts coalescing system of the invention comprises a first calculating device, a packet header parser, a second calculating device, and an interrupt controller. The first calculating device is used for calculating packet information of a plurality of packets. The packet header parser is used for recognizing the type of service field in each packet and for generating a minimum delay control signal. The second calculating device is used for determining a coalescing interrupt number signal according to the packet information and the minimum delay control signal. The interrupt controller is used for transmitting an interrupt control signal to process the packet according to the coalescing interrupt number signal. The system of the invention can process the minimum delay packet in a minimum delay time so as to reduce the delay time of the minimum delay packet and the average delay time of the packets and to avoid the miss owing to the delay of the packet.
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Wang Jun-Yao
Wang Wen-Fong
Dang Khanh
Industrial Technology Research Institute
Volentine & Whitt PLLC
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