Adaptive idle timer for a memory device

Details Adaptive idle timer for a memory device Adaptive idle timer for a memory device

2005-06-21

2005-06-21

Moazzami, Nasser (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

Reexamination Certificate

active

06910114

ABSTRACT:
Embodiments of the present invention provide for adaptively tuning the memory idle timer value in real time. Selected memory idle clock cycles are sampled to dynamically determine an optimized memory idle timer value. To optimize latency during sampling, the number of page hits (NPH) and number of page misses (NPM) are multiplied by weighted values WPHand WPM, respectively, such that the weighted function (WPH*NPH)−(WPM*NPM) is maximized. The weight associated with a page miss (WPM) is greater than the weight associated with a page hit (WPH), resulting in a bigger penalty for a page miss than a page hit. The selected setting is continuously optimized.

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