Adaptive elasticity FIFO

Details Adaptive elasticity FIFO Adaptive elasticity FIFO

2005-06-20

2008-12-02

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S502000, C713S503000, C710S052000, C710S054000, C710S055000, C710S056000, C710S057000

Reexamination Certificate

active

07461284

ABSTRACT:
Disclosed is a method for minimizing the buffer size of an elasticity FIFO queue when synchronizing data between two clock domains. Data communication is typically sent by a transmitter device to a receiver device. The transmitted data signal includes an embedded clock signal and null data characters, as specified by the data communication signal protocol. A null character indicates an empty data frame and is included as part of most standard communication protocols. An embodiment skips one or more null characters from the elasticity FIFO queue during a single clock cycle when it is detected that the write pointer is catching up to the read pointer. By skipping multiple null characters during a single write cycle, the read pointer is moved ahead by one or more queue locations and the write pointer is insured to not catch up to the read pointer for a wider variation in frequencies between a transmitter and receiver than is normally possible. Typically, the elasticity FIFO queue size must be increased in order to support a larger frequency variation. By reducing the need to increase the elasticity FIFO queue size, the gate count and area needed for the elasticity FIFO queue on the silicon chip of the receiver is reduced, thus, reducing the cost contribution of the elasticity FIFO queue to the receiver device. Skipping null characters also reduces the latency time between a write and the associated read of a non-null data character.

REFERENCES:
patent: 5623699 (1997-04-01), Blakeslee
patent: 6460130 (2002-10-01), Trull et al.

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