Adaptive de-skew clock generation

Details Adaptive de-skew clock generation Adaptive de-skew clock generation

2005-07-12

2005-07-12

Bocure, Tesfaldet (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C370S519000, C713S503000

Reexamination Certificate

active

06917660

ABSTRACT:
A signal delay circuit that compensates for other delays introduced within the signal delay circuit itself. A delay-locked loop may produce multiple delayed clock signals, each having a defined phase difference with respect to, and representing a different delay from, a reference clock. A synchronization circuit may determine a first selection value that selects a first delayed clock whose delay compensates for the propagation delays created in a selection circuit. A selection circuit may add a specified offset value to the first selection value to produce a second selection value, and use the second selection value to select a second delayed clock whose delay approximates the sum of the internal delay of the selection circuit and the delay specified by the offset value.

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Guang-Kaai Dehng, June-Ming Hsu, Ching-Yuan Yang, Shen-Iuan Liu, “Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop”, Aug. 2000, IEEE Journal Of Solid-State Circuits, vol. 8, No. 8.

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