Adaptive clock-less equalizer circuit

Details Adaptive clock-less equalizer circuit Adaptive clock-less equalizer circuit

2008-07-29

2008-07-29

Ha, Dac V (Department: 2611)

Pulse or digital communications

Equalizers

Automatic

Reexamination Certificate

active

10678999

ABSTRACT:
A system and method for equalizing a signal is provided. In one implementation, the method includes generating a partially equalized signal from an input signal based on a plurality of coefficients associated with a feed-forward equalizer (FFE); generating decoded bit values based on the partially equalized signal, the decoded bit values being an equalized output signal; measuring error in the partially equalized signal; and adjusting the coefficients associated with the feed-forward equalizer (FFE) based on the error measured in the partially equalized signal. Values of the coefficient are not used to adjust of the coefficients associated with the feed-forward equalizer (FFE).

REFERENCES:
patent: 4594591 (1986-06-01), Burke
patent: 5028784 (1991-07-01), Arakawa et al.
patent: 2001/0043650 (2001-11-01), Sommer et al.
patent: 2004/0090892 (2004-05-01), Kadlec
patent: 2005/0019042 (2005-01-01), Kaneda et al.

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