Adaptive calibration technique for high speed memory devices

Details Adaptive calibration technique for high speed memory devices Adaptive calibration technique for high speed memory devices

2000-11-30

2002-11-19

Robertson, David L. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C714S042000, C365S212000

Reexamination Certificate

active

06484232

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to memory systems that include high speed memory devices. More particularly, the present invention relates to memory systems, such as Direct Rambus Dynamic Random Access Memory (RDRAM), that require calibration cycles to insure proper operation. Still more particularly, the present invention relates to a memory system that includes a temperature sensor associated with high speed memory devices, and a memory controller that modifies the frequency of calibration cycles based on the readings received from the temperature sensor.
2. Background of the Invention
Almost all computer systems include a processor and a system memory. The system memory functions as the working memory of the computer system, where data is stored that has been or will be used by the processor and other system components. The system memory typically includes banks of dynamic random access memory (DRAM) circuits. According to normal convention, a memory controller interfaces the processor to a memory bus that connects electrically to the DRAM circuits. While DRAM circuits have become increasingly faster, the speed of memory systems typically lags behind the speed of the processor. Because of the large quantity of data that is stored in the system memory, it may at times be a bottleneck that slows down the performance of the computer system. Because of this disparity in speed, in most computer systems the processor must wait for data to be stored (“written”) and retrieved (“read”) from DRAM memory. The more wait states that a processor encounters, the slower the performance of the computer system.
The main memory provides storage for a large number of instructions and/or a large amount of data for use by the processor, providing faster access to the instructions and/or data than would otherwise be achieved if the processor were forced to retrieve data from a disk or drive. However, the access times of modem RAMs are significantly longer than the clock cycle period of modem processors. To minimize the latency of the system, various high-speed memory devices have been introduced to the market. An example of such a high-speed memory device is the Direct RDRAM device developed by Rambus. See “RAMBUS Preliminary Information Direct RDRAM™”, Document DL0060 Version 1.01; “Direct Rambus™ RIMM™ Module Specification Version 1.0”, Document SL-0006-100; “Rambus® RIMM™ Module (with 128/144 Mb RDRAMs)” Document DL00084, Version 1.1, which are incorporated by reference herein. As indicated in the Rambus specifications, the Direct RDRAM memory is capable of transferring 1.6 GB per second per DRAM device.
Each Direct RDRAM device typically includes 32 banks, with 512 rows per bank, although other size RDRAM devices may be available. Depending on the size of the RDRAM device, each row (or page) typically has either 1 kilobyte or 2 kilobytes of memory storage capability. The Direct RDRAM devices are arranged in channels, with each channel currently capable of supporting up to 16 Direct RDRAM devices. One or more Direct RDRAM devices may be packaged in Rambus In-line Memory Modules (RIMMs). Multiple channels may be provided in a computer system to expand the memory capabilities of the system.
While Direct RDRAM and similar memory devices are theoretically capable of operating at very high speeds, they exhibit certain severe operating constraints that can significantly degrade performance. To achieve the high operational speeds, the memory devices have very precise timing requirements, with very little margin or tolerance for deviation. Parameters for read transactions will be discussed briefly to illustrate some of the timing issues.
As shown in
FIG. 1
, the Direct RDRAM couples to a memory controller (which includes a Rambus ASIC Cell or “RAC”) via two clock signal lines, three Row signal lines, five Column signal lines, and two data busses. The clock lines include a Clock-to-Master (CTM) line, and a Clock-from-Master (CFM) line that are used to synchronize signals to the memory controller and from the memory controller, respectively. The Row signal lines and Column signal lines form part of a control and address bus (RQ bus) that typically includes eight lines. The Row signal lines (ROW
2
. . . ROW
0
) are used primarily to control row accesses in the memory, while the Column signal lines (COL
4
. . . COL
0
) are used primarily to control column accesses. The data busses include a DQA (DQA
8
. . . DQ
0
) and a DQB data bus (DQB
8
. . . DQ
0
), that couple to sense amps on opposite sides of the memory banks.
The three Row lines identify which of the 512 possible rows is addressed by presenting nine row bits (R
8
. . . R
0
) in three subsequent half clock cycles (2
9
=512), as shown in FIG.
2
. The device row (DR) bits (DR
3
. . . DR
0
) identify which of the 16 possible memory devices is targeted, while the five Bank row (BR) bits (BR
4
. . . BR
0
) identify which of the 32 banks is targeted in that device. Similarly, and as shown in
FIG. 3
, the five Column lines identify which of the 64 possible columns is being addressed by presenting 7 column bits (C
6
. . . C
0
) in two subsequent half cycles. The device column (DC) bits (DC
4
. . . DC
0
) identify which of the memory devices is targeted, while the five Bank column (BC) bits (BC
4
. . . BC
0
) identify which of the 32 banks is targeted.
Referring to
FIG. 4A
, a read transaction is performed on a Direct RDRAM device by asserting an Activate command in a ROWA (row activate) packet on the Row signal lines. The Activate command identifies the device, bank and row address of the targeted memory location. A time period t
RCD
later, a Read command is issued in a Column operation (COLC) packet on the Column signal lines. The Read command identifies the device, bank, and column address of the targeted memory location. Thus, the Activate command and Read command in conjunction identify the specific memory location being accessed, with the Activate command identifying the row, and the Read command identifying the column.
A time period t
CAC
after the Read command, a read data dualoct (16 bytes) is returned by the targeted memory device. The time period t
CAC
includes one to five cycles of round-trip propagation delay on the channel. According to current Rambus specifications, the t
CAC
period may be programmed to a range of values that vary from 7 t
CYCLE
to 12 t
CYCLE
. The particular value selected for t
CAC
depends on the number of RDRAM devices on the channel and the RDRAM timing bin so that the round trip propagation delay is equalized for all memory devices. Thus, based on the programmed timing parameters, the memory controller expects that during read cycles, all memory devices will return read data within a specified number of clock cycles after the Read command is asserted. Failure to return data in accordance with these timing parameters will cause data corruption, and may result in failure of the memory system.
The above timing parameters for a read transaction is just one example of the critical nature of timing in a high speed memory device, where the delay of a few nanoseconds can result in data corruption. Unfortunately, high-speed memory devices such as Direct RDRAM have proven highly susceptible to temperature and other environmental conditions such as humidity. If such conditions change during operation, the round-trip propagation delay of the signals propagating between the memory controller and the memory devices will be affected. If the actual propagation delay varies from the programmed delay, the memory system may experience data corruption.
As shown in the example of
FIG. 4B
, a write transaction to an RDRAM memory device begins by activating a bank in a memory device with an Activate command in a ROW activate packet. A time period t
RCD
-t
RTR
later, a Write command issues in a Column operation packet, w

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