Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-04-01
2008-04-01
Shah, Sanjiv (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S133000, C711S158000, C711S213000
Reexamination Certificate
active
07353339
ABSTRACT:
Provided are techniques for cache management. An incoming request to access a first data block is received. A probability of how likely a second data block may be accessed based on the access of the first data block is determined. Whether the probability exceeds a read ahead threshold is determined. The second data block is prefetched in response to determining that the probability exceeds the read ahead threshold.
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Komarla Eshwari P.
Zimmer Vincent J.
Davda Janaki K.
Intel Corporation
Konrad Raynes & Victor LLP
Shah Sanjiv
Yu Jae Un
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