Adaptive cache compression system

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

07412564

ABSTRACT:
Data in a cache is selectively compressed based on predictions as to whether the benefit of compression in reducing cache misses exceeds the cost of decompressing the compressed data. The prediction is based on an assessment of actual costs and benefits for previous instruction cycles of the same program providing dynamic and concurrent adjustment of compression to maximize the benefits of compression in a variety of applications.

REFERENCES:
patent: 5671389 (1997-09-01), Saliba
patent: 6324621 (2001-11-01), Singh et al.
patent: 6735673 (2004-05-01), Kever
patent: 7225297 (2007-05-01), Heil
patent: 2002/0085631 (2002-07-01), Engwer
Luca Benini, Davide Bruni, Alberto Macii, and Enrico Macii, Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors. In Proceedings of the IEEE 2002 Design Automation and Test in Europe, pp. 449-453, Mar. 2002.
Luca Benini, Davide Bruni, Bruno Ricco, Alberto Macii, and Enrico Macii. An Adaptive Data Compression Scheme for Memory Traffic Minimization in Processor-Based Systems. In Proceedings of the IEEE International Conference on Circuits and Systems, ICCAS-02, pp. 866-869, May 2002.
Daniel Citron and Larry Rudolph. Creating a Wider Bus Using Caching Techniques. In Proceedings of the First IEEE Symposium on High-Performance Computer Architecture, pp. 90-99, Feb. 1995.
Matthew Farrens and Arvin Park. Dynamic Base Register Caching: A Technique for Reducing Address Bus Width. In Proceedings of the 18th Annual Internatonal Symposium on Computer Architecture, pp. 128-137, May 1991.
Peter Franaszek, John Robinson, and Joy Thomas. Parallel Compression with Cooperative Dictionary Construction. In Proceedings of the Data Compression Conference, DCC '96, pp. 200-209, Mar. 1996.
Erik G. Hallnor and Steven K. Reinhardt. A Fully Associative Software-Managed Cache Design. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pp. 107-116, Jun. 2000.
Erik G. Hallnor and Steven K. Reinhardt. A Compressed Memory Hierarchy Using an Indirect Cache. Technical Report CSE-TR-488-04, University of Michigan, Jun. 2004.
Morten Kjelso, Mark Gooch, and Simon Jones. Design and Performance of a Main Memory Hardware Data Compressor. In Proceedings of the 22nd EUROMICRO Conference, Sep. 1996.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Adaptive cache compression system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Adaptive cache compression system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Adaptive cache compression system will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4018616

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.