Adaptive bus arbitration using history buffer

Details Adaptive bus arbitration using history buffer Adaptive bus arbitration using history buffer

1999-09-29

2003-01-28

Dharia, Rupal (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S240000

Reexamination Certificate

active

06513082

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to time division multiplexed (TDM) digital systems. More particularly, it relates to arbitration methods and apparatus in an extended digital system.
2. Background of Related Art
Numerous digital devices are utilized by consumers throughout the world. In each of these devices, digital samples are passed between individual components, often using time division multiplexed (TDM) techniques over serial and/or parallel busses between the components. Arbitration for use of a system bus for passing these digital samples is typically controlled by an arbiter responsible for the system bus.
A TDM data stream typically comprises a repeating data cycle or frame, with each data frame being divided into a plurality of time slots. The data frame repeats over and over, but typically with new data samples in relevant time slots for each new cycle or frame of data. The data frames are conventionally synchronized with a frame synchronization signal or similar signal.
In a more general sense, time slots can relate to the time-shared usage of a system bus, e.g., a 32 bit parallel system bus. During an assigned time slot, a particular device can make exclusive use of the system bus up to the length of time allowed by a pre-determined configuration.
Time slots may be of any particular length, and separate time slots in a particular data frame may have different lengths.
Depending upon the needs of a particular application, conventional input and output channels of TDM system buses typically have fixed locations within a data frame assigned by a master controller or processor in the system.
A significant amount of flexibility can be provided using a time slot which may be used by any of a plurality of devices. For instance, if one particular device on a system bus requires a significant amount of time (and thus a long time slot) to perform a particular activity, then it would conventionally request bus access from the master controller. The conventional master controller assigns use of the TDM system bus in accordance with a given set of arbitration rules, e.g., a round-robin allocation, or an interrupt driven access request resulting in a first come, first served allocation.
The more flexibility in the use of a TDM system bus, the wider the market applications. In conventional systems, the designer typically implements this flexibility within the program code of the master controller of the system. In such systems, the master controller or processor allows access to a TDM system bus in accordance with its established arbitration rules. Flexibility is provided in such conventional devices by allowing the controller to change the length of access for any particular requesting device as desired.
Conventional system bus arbitration requires substantial resources or overhead of the master controller, which only increase as the complications of the system become greater. This is particularly true in multiple processor based systems, where communication data traffic between the processors increases as requests for access to the arbitrated system bus increase. Moreover, as the size of systems increases and as the number of agents on a particular system bus grows, the arbitration processing becomes enormous. This increased overhead results in a decreased amount of processing available for other tasks.
Conventional system arbiters exist, but are typically a priority-based super arbiter inside a super core or microcontroller.
There is thus a need for a more flexible arbitration architecture allowing use of a TDM system bus without requiring the significant overhead otherwise conventionally required in a master controller.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, an adaptive system bus arbiter and bus monitor comprises a bus monitor, in communication with a system bus, to monitor usage of a system bus by a plurality of agents, and an arbiter, in communication with the plurality of agents, to adaptively grant usage of the system bus to the plurality of agents based on monitored usage of the system bus by respective ones of the plurality of agents.


REFERENCES:
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patent: 5452330 (1995-09-01), Goldstein
patent: 5754836 (1998-05-01), Rehl
patent: 2120429 (1983-11-01), None

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