Adaptive adjustment of constraints during PLD placement...

Details Adaptive adjustment of constraints during PLD placement... Adaptive adjustment of constraints during PLD placement...

2006-02-14

2006-02-14

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07000210

ABSTRACT:
A technique for mapping a plurality of configurable logic blocks in a programmable logic device, such as a field-programmable gate array (FPGA). The method includes adaptively adjusting one or more customer-specified constraints and can be implemented, for example, using a simulated annealing algorithm. During the refinement of the placement (i.e., assignment) of logic blocks in an FPGA, one or more constraints are adjusted by either selecting a customer-specified constraint value or specifying a new constraint value derived based on the actual circuit performance. The method provides substantial savings of computer time compared to the prior art placement methods and improves circuit performance, e.g., by enabling higher circuit operation frequencies.

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“Timing-driven Placement Based on Partitioning with Dynamic Cut-net Control,” by Shih-Lian Ou and Massoud Pedram, Department of EE-Systems, University of Southern California, Los Angeles, CA 90089, 2000.

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